MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 96
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 96 of 481
- Download datasheet (2Mb)
System Integration Block (SIB)
After system reset, the FC field in BR3–BR0 defaults to supervisor program space (FC =
110) to select a ROM device containing the reset vector. Because of the priority mechanism
and the EN bit, only the CS0 line is active after a system reset.
Bits 12–2—Base Address
RW—Read/Write
On write protect violation cycles (RW = 0 and MRW = 1), BERR will be generated if WPVE
is set, and WPV will be set.
If the write protect mechanism is used by an external master, the R/W low to AS asserted
timing should be 16 ns minimum.
3-46
address match exists within its address space and, therefore, whether to assert the chip-
select line.
These bits are used to set the starting address of a particular address space. The address
compare logic uses only A23–A13 to cause an address match within its block size. The
base address should be located on a block boundary. For example, if the block size is 64k
bytes, then the base address should be a multiple of 64k.
After system reset, the base address defaults to zero to select a ROM device on which
the reset vector resides. All base address values default to zero on system reset, but, be-
cause of the priority mechanism, only CS0 will be active.
After system reset, this bit defaults to zero (read-only operation).
111 = Not supported; reserved. Chip select will not assert if this value is chosen.
110 = Value may be used.
000 = Value may be used.
0 = The chip-select line is asserted for read operations only.
1 = The chip-select line is asserted for write operations only.
•
•
•
The FC bits can be masked and ignored by the chip-select logic
using CFC in the OR.
All address bits can be masked and ignored by the chip-select
logic through the base address mask in the OR.
This bit can be masked and ignored by the read-write compare
logic, as determined by MRW in the OR. The line is then assert-
ed for both read and write cycles.
MC68302 USER’S MANUAL
NOTE
NOTE
NOTE
MOTOROLA
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