MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 56
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 56 of 481
- Download datasheet (2Mb)
System Integration Block (SIB)
RST—Software Reset
STR—Start Operation
3.1.2.2 Source Address Pointer Register (SAPR)
The SAPR is a 32-bit register.
The SAPR contains 24 (A23–A0) address bits of the source operand used by the IDMA to
access memory or memory-mapped peripheral controller registers. During the IDMA read
cycle, the address on the master address bus is driven from this register. The SAPR may
be programmed by the SAPI bit to be incremented or remain constant after each operand
transfer.
The register is incremented using unsigned arithmetic and will roll over if an overflow occurs.
For example, if a register contains $00FFFFFF and is incremented by one, it will roll over to
$00000000. This register can be incremented by one or two, depending on the SSIZE bit
and the starting address in this register.
3.1.2.3 Destination Address Pointer Register (DAPR)
The DAPR is a 32-bit register.
3-6
31
31
This bit will reset the IDMA to the same state as an external reset. The IDMA clears RST
when the reset is complete.
This bit starts the IDMA transfer if the REQG bits are programmed for an internal request.
(The IDMA begins requesting the M68000 bus one clock after STR is set.) If the REQG
bits are programmed for an external request, this bit must be set before the IDMA will rec-
ognize the first request on the DREQ input.
0 = Normal operation
1 = The channel aborts any external pending or running bus cycles and terminates
0 = Stop channel; clearing this bit will cause the IDMA to stop transferring data at
1 = Start channel; setting this bit will allow the IDMA to start (or continue if previously
RESERVED
RESERVED
channel operation. Setting RST clears all bits in the CSR and CMR.
the end of the current operand transfer. The IDMA internal state is not altered.
stopped) transferring data.
These percentages are valid only when using internal limited re-
quest generation (REQG = 00).
STR is cleared automatically when the transfer is complete.
24
24
23
23
MC68302 USER’S MANUAL
NOTE
NOTE
DESTINATION ADDRESS POINTER
SOURCE ADDRESS POINTER
MOTOROLA
0
0
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