MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 233

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

I—Interrupt
L—Last
TC—Tx CRC
When the last bit is not set but TC is set (e.g., in a header buffer), the DDCMP controller will
append the next buffer immediately following the CRC sequence. The preset value for the
CRC16 calculation is located in the PCRC register and should be initialized to all zeros or
all ones.
OL—Optional Last
Bits 8–2—Reserved for future use.
UN—Underrun
CT—CTS Lost
MOTOROLA
This bit allows the user to transmit abutted messages in DDCMP.
The following status bits are written by the DDCMP controller after it has finished trans-
mitting the associated data buffer.
The DDCMP controller encountered a transmitter underrun condition while transmitting
the associated data buffer.
CTS in NMSI mode or grant in IDL/GCI mode was lost during message transmission.
0 = No interrupt is generated after this buffer has been serviced.
1 = Either TX or TXE in the DDCMP event register will be set when this buffer has been
0 = This buffer is not the last in the message.
1 = The last bit is set by the processor to indicate that this buffer is the last buffer in the
0 = Do not transmit a CRC sequence after the buffer's last data byte.
1 = Transmit a CRC16 sequence after the buffer's last data byte.
0 = Normal operation. The SYNF bit in the DDCMP mode register determines the pat-
1 = Abutted messages. The CP checks the ready bit of the next Tx BD after processing
serviced by the DDCMP controller, which can cause interrupts.
current message.
tern transmitted between messages.
the current BD, and, if set, abuts the next message to the current message. If the
ready bit is not set, the SYNF bit determines the transmitted pattern.
The DDCMP controller checks the TC bit, not the last bit, to de-
termine whether to append the CRC sequence. The DDCMP
controller will transmit the programmable number of SYN1–
SYN2 pairs before transmitting the next buffer (message) when
the last bit is set.
This error can occur only on synchronous links.
MC68302 USER’S MANUAL
NOTE
NOTE
Communications Processor (CP)
4-113