MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 82

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
Table 3-7 shows the dedicated function of each pin. The third column shows the input to the
peripheral when the pin is used as a general-purpose I/O pin.
3.3.2.2 PB11–PB8
PB11–PB8 are four general-purpose I/O pins continuously available as general-purpose I/
O pins and, therefore, are not referenced in the PBCNT. PB8 operates like PB11–PB9 ex-
cept that it can also be used as the DRAM refresh controller request pin, as selected in the
system control register (SCR).
The direction of each pin is determined by the corresponding bit in the PBDDR. The port pin
is configured as an input if the corresponding PBDDR bit is cleared; it is configured as an
output if the corresponding PBDDR bit is set. PBDDR11–PBDDR8 are cleared on total sys-
tem reset, configuring all PB11–PB8 pins as general-purpose input pins. (Note that the port
pins do not have internal pullup resistors). The GIMR is also cleared on total system reset
so that if any PB11–PB8 pin is left floating it will not cause a spurious interrupt.
The PB11–PB8 pins are accessed through the PBDAT. Data written to PBDAT11–PBDAT8
is stored in an output latch. If the port pin is configured as an output, the output latch data is
gated onto the port pin. In this case, when PBDAT11–PBDAT8 is read, the contents of the
output latch associated with the output port pin are read. If a port B pin is configured as an
input, data written to PBDAT is still stored in the output latch but is prevented from reaching
the port pin. In this case, when PBDAT is read, the state of the port pin is read.
When a PB11–PB8 pin is configured as an input, a high-to-low change will cause an inter-
rupt request signal to be sent to the IMP interrupt controller. Each of the four interrupt re-
quests is associated with a fixed internal interrupt priority level within level 4. (The priority at
which each bit requests an interrupt is detailed in Table 3-4.) Each request can be masked
independently in the IMP interrupt controller by clearing the appropriate bit in the IMR
(PB11–PB8). The input signals to PB11–PB8 must meet specifications 190 and 191 shown
in Table 6.16 of the AC Electrical Specifications.
3.3.3 I/O Port Registers
The I/O port consists of three memory-mapped read-write 16-bit registers for port A and
three memory-mapped read-write 16-bit registers for port B. Refer to Figure 3-6 for the I/O
port registers. The reserved bits are read as zeros.
3-32
PBCNT Bit = 1
Pin Function
TOUT1
TOUT2
WDOG
IACK7
IACK6
IACK1
TIN1
TIN2
Table 3-7. Port B Pin Functions
MC68302 USER’S MANUAL
PBCNT Bit = 0
Pin Function
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Control and Timers
Input to Interrupt
GND
GND
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MOTOROLA