MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 336

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

SCC Performance
with a faster serial clock (subject to the clocking limits of the SCC mentioned previously) as
long as the bit rate over a 9-bit (17-bit period for HDLC or transparent) period averages out
to 1.67 Mbps.
A-2
NOTES:
1. SCC performance calculation example with a 16.67-MHz system clock:
2. "Difficult" buffer parameters were chosen as shown below. Use of less difficult parameters does not significantly
4. The last address or control character in the table was checked.
5. For the DDCMP, the frame length was 6 and 59 bytes for the two BDs.
6. When the performance of a high-speed channel together with a low-speed channel was measured, the high-speed
3. The external RAM access time is two wait states. As a general rule, the addition of a wait state only decreases
3 BISYNC
3 DDCMP
One HDLC channel can operate with a ratio of 1:9. Thus,16.67-MHz/9 gives 1.8 Mbps, and a 20-MHz system clock
gives 2.22 Mbps.
improve performance. The SCCs transmit and receive from/into multiple buffers per frame. Tx BD 1 address is ODD
and has 59 bytes; whereas, the Tx BD2 address is EVEN and has 60 bytes. In HDLC mode, Rx BD1 address is
EVEN, but is ODD in other modes. Rx BD1 is (frame length-1) bytes long and Rx BD2 is 1 byte long.
maximum performance by about 1%.
1 Transp
2 Transp
3 Transp
Number
1 HDLC
1 HDLC
2 HDLC
3 HDLC
1 HDLC
2 HDLC
3 UART
High-Speed Channels
Frequency Ratio
1:2.5
1:22
1:37
1:10
1:10
1:10
1:10
1:10
1:22
1:23
1:24
1:24
1:25
1:23
1:24
1:23
1:24
1:60
1:75
1:10
1:23
1:35
1:7
1:9
1:9
1:9
1:9
1:9
1:9
1:9
MC68302 USER’S MANUAL
Number
BISYNC
BISYNC
BISYNC
2 UART
2 UART
DDCMP
DDCMP
2 HDLC
2 HDLC
2 HDLC
DDCMP
DDCMP
UART
HDLC
HDLC
UART
UART
UART
HDLC
HDLC
—
—
—
—
—
—
—
—
—
—
Low-Speed Channels
Frequency Ratio
1:396 (*16)
1:329 (*16)
1:305 (*16)
1:20 (*16)
1:10 (*16)
1:128,238
1:24 (*16)
1:1151
1:366
1:241
1:224
1:128
1:496
1:177
1:229
1:241
1:113
1:98
1:98
1:57
—
—
—
—
—
—
—
—
—
—
Buffers in Dual-Port RAM
Half-Duplex Bisync
Half-Duplex Bisync
Half-Duplex Bisync
UART Uses 16x Clock
Half-Duplex Bisync
Comments/Restrictions
MOTOROLA