MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 347
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 347 of 481
- Download datasheet (2Mb)
APPENDIX C
RISC MICROCODE FROM RAM
The MC68302 RISC processor has an option to execute microcode from the 576-byte user
RAM in the on-chip dual-port RAM. In this mode, the 576-byte user RAM cannot be access-
ed by the M68000 core or other M68000 bus masters. Also in this mode, port A pins are op-
tionally available to the RlSC processor as well as the M68000 core. Figure C-1 shows these
resulting changes.
Once the microcode has been loaded into the dual-port RAM by the M68000 core or other
bus master, the microcode from RAM option is enabled in the reserved register at location
$0F8. When the user writes $0001 to location $0F8, the RISC processor will execute micro-
code from RAM once the CP is reset in the command register. Hereafter, the RISC proces-
sor can freely address both the dual-port RAM and its own private ROM.
MOTOROLA
PB8 REQUEST
CONTROLLER
RISC
CR REQUEST
SERIAL
SERVICE
REQUESTS
Figure C-1. CP Architecture Running RAM Microcode
CHANNELS
CR
OTHER
SERIAL
CHANNELS
6 SDMA
FIFO
PERIPHERAL BUS
SCC1
MC68302 USER’S MANUAL
FIFO
MICROCODE
ROM
M68000 BUS
PHYSICAL INTERFACE
SERIAL CHANNELS
FIFO
SCC2
FIFO
MICROCODE
DUAL-PORT
RAM
DUAL-PORT RAM
FIFO
SCC3
PARAMETER
FIFO
RAM
REGS
PHY
I/F
REGS
PORT
SCC
H/W
PINS
I/O
A
C-1
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