MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 348

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

RISC Microcode from RAM
Microcode for a new application or protocol is developed only under special arrangement
and coordination with Motorola.
Some RAM microcode routines are also available for purchase. The following is an overview
of available functions. Contact a Motorola sales office for detailed specifications of the mi-
crocode routines.
C.1 SS7 PROTOCOL SUPPORT
The HDLC routines are enhanced and extended to provide special Signaling System #7
(SS7) support. In addition to the HDLC features of the MC68302, the following key features
are included:
Any or all three SCCs can become an SS7 protocol controller. The SS7 microcode increas-
es that portion of layer 2 SS7 already supported by the HDLC features in the MC68302. This
implementation of SS7, however, is not a complete layer 2 implementation. Rather, the ad-
ditional features included in the SS7 controller are those that would have been especially
difficult and/or time-consuming to support by the M68000 core alone, due to their continuous
or real-time nature.
C.2 CENTRONICS TRANSMISSION CONTROLLER
The RISC processor implements a Centronics parallel interface using the PA7–PA0, PA12–
PA8, and the PA15 parallel l/O pins. All SCC channels and protocols, including DRAM re-
fresh, are supported concurrently with this feature, but SCC2, if used, must be configured in
a multiplexed mode, and several of its buffer descriptors are used by the Centronics inter-
face. Once a buffer is configured in memory, the protocol handles the movement of all data
from the buffer to the interface.
This package implements the transmitter function of the Centronics interface. (Another
package can implement the receiver function.)
The features supported are as follows:
C-2
• Automatic Fill-In Signal Unit (FISU) Transmission and Reception
• Automatic Link Status Signal Unit (LSSU) Retransmission
• Octet Counting Mode Support
• Two Signal Unit Counters (error and error-free signal units)
• Three Flexible Data Buffers for Transmission
• Controls the Eight Data Lines and Data Strobe
• Supports the PE, SLCT, FAULT, BUSY and INPUT PRIME Conditions
• Supports the Start Print and Stop Print Commands
• Interrupts May Be Generated After Each Buffer or Upon an Error Condition
• Transmission Rates up to 260 kbytes/sec.
MC68302 USER’S MANUAL
MOTOROLA