MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 251

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

OFFSET + 0
OFFSET + 2
OFFSET + 4
I—Interrupt
The following status bits are written by the CP after the received data has been placed into
the associated data buffer.
Bits 11–2—Reserved for future use. Should be written with zero by the user.
OV—Overrun
CD—Carrier Detect Lost
Data Length
Rx Buffer Pointer
4.5.16.9 Transparent Transmit Buffer Descriptor (Tx BD)
Data is presented to the CP for transmission on an SCC channel by arranging it in buffers
referenced by the channel's Tx BD table. The CP confirms transmission (or indicates error
conditions) using the BDs to inform the processor that the buffers have been serviced. The
Tx BD is shown in Figure 4-43.
OFFSET +6
The first word of the Tx BD contains status and control bits. These bits are prepared by the
user before transmission and are set by the CP after the buffer has been transmitted.
MOTOROLA
A receiver overrun occurred during reception.
The carrier detect signal was negated during buffer reception.
The data length is the number of octets that the CP has written into this BD's data buffer.
It is written only once by the CP as the buffer is closed.
The receive buffer pointer, which always points to the first location of the associated data
buffer, must be even. The buffer may reside in either internal or external memory.
0 = No interrupt is generated after this buffer has been used.
1 = When this buffer has been closed by the transparent controller, the RX bit in the
transparent event register will be set, which can cause an interrupt.
15
R
The actual buffer size should be greater than or equal to the
MRBLR.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
14
X
Figure 4-43. Transparent Transmit Buffer Descriptor
13
W
12
I
TX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
L
MC68302 USER’S MANUAL
10
—
NOTE
NOTE
—
9
DATA LENGTH
—
8
—
7
—
6
Communications Processor (CP)
—
5
—
4
—
3
—
2
UN
1
4-131
CT
0