MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 404
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
MC68302 Applications
Figure D-25 shows how CTS can be used in the NMSI transmit case. NTSYN and EXSYN
are set to enable transparent mode. Instead of software operation for CTS and CD, normal
(automatic) operation is chosen. RTS is asserted when the transmit FIFO is full. From then
on, data is held off until CTS is sampled low. From that sample point, there is a 3.5 TCLK
delay before the first bit of the data buffer is transmitted. Ones are transmitted until the first
bit of the data buffer is transmitted.
In the case shown in Figure D-25, it is important that CTS not go high for the duration of the
buffer transmission. If multiple buffers are all ready with their L bits cleared, transmission of
frames will continue back-to-back. If CTS negated during any of these buffers, transmission
will cease, and that buffer will report a CTS lost condition. Ones will be transmitted at that
time. Once a restart transmit command is given, transmission of the next buffer can begin
once CTS is reasserted.
Once CTS deasserts after RTS, the RTS-CTS protocol can begin again as soon as the next
buffer is made ready, but a minimum of 17 idle bits will occur between frames, regardless of
how soon CTS is reasserted. Remember that when EXSYN is set, CD (sync) must be low
for transmission to begin. In this case, it is grounded; whereas, in the following case, EXSYN
is actively switching.
Figure D-26 shows how CD (sync) can be used to control transmission. EXSYN and NTSYN
are once again set to enable transparent mode, and the L bit is set. Since software operation
mode (DIAG1 = 1 and DIAG0 = 1) is chosen, the CTS pin value is ignored. Once CD (sync)
is latched low, data begins transmission in 6.5 TCLKs. Notice that the rising edge of CD
(sync) and subsequent falling edges of CD (sync) (not shown) have no effect, since synchro-
nization has already been achieved.
D-54
CD (SYNC)
(OUTPUT)
(OUTPUT)
(INPUT)
(INPUT)
RCLK
TCLK
(I/O)
(I/O)
TXD
RTS
CTS
EXSYN = 1
NTSYN = 1
DIAG1-DIAG0 BITS = 00
L = 1 IN THE Tx BD
ONLY ONE Tx BD IS READY
Figure D-25. Using CTS In the NMSI Transmit Case
DATA READY TO TRANSMIT HERE
3.5 TCLKs
CTS SAMPLED AS LOW HERE
MC68302 USER’S MANUAL
FIRST BIT OF DATA
IN BUFFER.
LAST BIT OF DATA
MUST NOT BE NEGATED
UNTIL RTS IS NEGATED,
OR CTS LOST ERROR WILL
RESULT
MOTOROLA
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