MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 110

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
HWDCN–HWDCN0—Hardware Watchdog Count 2–0
3.8.7 Reducing Power Consumption
There are a number of ways to reduce power consumption on the IMP. They can be classi-
fied as general power-saving tips and low-power modes.
3.8.7.1 Power-Saving Tips
Without using any of the IMP low-power modes, power consumption may be reduced in the
following ways.
3.8.7.2 Low-Power (Standby) Modes
The IMP also supports several types of low-power modes. The low-power modes on the IMP
are used when no processing is required from the M68000 core and when it is desirable to
reduce system power consumption to its minimum value. All low-power modes are entered
by first setting the low-power enable (LPEN) bit, and then executing the M68000 STOP in-
struction.
3-60
After system reset, these bits default to all ones; thus, BERR will be asserted after 1 ms
for a 16-MHz system clock.
1. The system clock frequency of the IMP may be reduced to the lower limit of its oper-
2. When not used, the SCCs should be disabled by clearing the ENT and ENR bits in the
3. If not needed, the SCC baud rate generators should be disabled or caused to clock at
4. The two general-purpose timer prescalers should be set to the maximum divider value,
5. Any unneeded peripheral output pins that are multiplexed with parallel I/O pins should
000 = BERR is asserted after 128 clock cycles (8 s, 16-MHz clock)
001 = BERR is asserted after 256 clock cycles (16 s, 16-MHz clock)
010 = BERR is asserted after 512 clock cycles (32 s, 16-MHz clock)
011 = BERR is asserted after 1K clock cycles (64 s, 16-MHz clock)
100 = BERR is asserted after 2K clock cycles (128 s, 16-MHz clock)
101 = BERR is asserted after 4K clock cycles (256 s, 16-MHz clock)
110 = BERR is asserted after 8K clock cycles (512 s, 16-MHz clock)
111 = BERR is asserted after 16K clock cycles (1 ms, 16-MHz clock)
ating frequency range (e.g., 8 MHz) as specified in Section 6 Electrical Characteris-
tics.
SCM registers.
a low frequency. The baud rate generators are initialized to a very fast clock rate after
reset, which can be reduced by programming the SCON register.
and the timers should be disabled if not used.
be left configured as parallel I/O pins. The smaller the number of output transistors
switching, the less current used.
Successive timeouts of the hardware watchdog may vary slight-
ly in length. The counter resolution is 16 clock cycles.
MC68302 USER’S MANUAL
NOTE
MOTOROLA