MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 133

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

In addition to the 144-kbps ISDN 2B + D channels, IDL provides channels for maintenance
and auxiliary bandwidth. The IDL bus has five channels:
The IMP supports all five channels of the IDL bus. The following table shows where each
channel can be routed. The two B channels can be concatenated and routed to the same
SCC channel.
The IMP supports the request-grant method for contention detection on the D channel.
When the IMP has data to transmit on the D channel, it asserts L1RQ. The physical layer
device monitors the physical layer bus for activity on the D channel and indicates that the
channel is free by asserting L1GR. The IMP samples the L1GR signal when L1SY1 is as-
serted. If L1GR is high (active), the IMP transmits the first zero of the opening flag in the first
bit of the D channel. If a collision is detected on the D channel, the physical layer device ne-
gates L1GR. The IMP then stops its transmission and retransmits the frame when L1GR is
asserted again. This is handled automatically for the first two buffers of the frame.
MOTOROLA
L1CLK
L1TXD
L1RXD
L1SY1
L1RQ
L1GR
SDS1
SDS2
B1
B2
D
M
A
The IDL bus signals, L1TXD and L1RXD, require pull-up resis-
tors in order to ensure proper operation with transceivers.
IDL clock; input to the IMP.
IDL transmit data; output from the IMP. Valid only for the bits that
are supported by the IDL; three-stated otherwise.
IDL receive data; input to the IMP. Valid for the 20 bits of the IDL;
ignored for other signals that may be present.
IDL SYNC signal; input to the IMP. This signal indicates that the
20 clock periods following the pulse designate the IDL frame.
Request permission to transmit on the D channel; output from the
IMP.
Grant permission to transmit on the D channel; input to the IMP.
Serial data strobe 1
Serial data strobe 2
64-kbps Bearer Channel
64-kbps Bearer Channel
16-kbps Signaling Channel
8-kbps Maintenance Channel (not required by IDL)
8-kbps Auxiliary Channel (not required by IDL)
IDL Channel
MC68302 USER’S MANUAL
B1
B2
M
D
A
NOTE
SCC1, SCC2, SCC3
SCC1, SCC2, SCC3
SCC1, SCC2, SCC3
SMC1
SMC2
Serial Controllers
Communications Processor (CP)
4-13