MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 257

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.6.2 SCP Transmit/Receive Buffer Descriptor
The transmit/receive BD contains the data to be transmitted (written by the M68000 core)
and the received data (written by the SCP). The done (D) bit indicates that the received data
is valid and is cleared by the SCP.
4.6.3 SCP Transmit/Receive Processing
The IMP SCP always functions in the master mode. Thus, in a typical exchange of messag-
es, the IMP transmits a message to an external peripheral (SCP slave) which, in turn, sends
back a reply. When the IMP works with more than one slave, it can use the general-purpose
parallel I/O pins as enable (select) signals. To begin the data exchange, the M68000 core
writes the data to be transmitted into the transmit/receive BD, and sets the done bit. The
M68000 core should then set the start transmit (STR) bit in the SPMODE register to start
transmission of data. STR is cleared by hardware after one system clock cycle.
Upon recognizing the STR bit, the SCP also begins receiving eight bits of data. It writes the
data into the transmit/receive BD, clears the done bit, and issues a maskable interrupt to the
IMP interrupt controller. When working in a polled environment, the done bit should be set
MOTOROLA
15
D
14
BRG3
RESERVED
Figure 4-45. SCP vs. SCC Pin Multiplexing
SCC3
BRG
BRG
SCP
MC68302 USER’S MANUAL
SPRXD
SPTXD
SPCLK
MC68302
CTS3
RTS3
CD3
8
EN
BIT
7
PLEXER
MULTI-
EN
Communications Processor (CP)
NMSI 3 INTERFACE
RXD3
TXD3
RCLK3
TCLK3
CTS3/SPRXD
RTS3/SPTXD
CD3/SPCLK
DATA
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0