MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 270

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Signal Description
HALT—Halt
BERR—Bus Error
BUSW—Bus Width Select
DISCPU—Disable CPU (M68000 core)
5-6
Besides the total system reset and the RESET instruction, some of the MC68302 periph-
erals have reset bits in one of their registers that cause that particular peripheral to be re-
set to the same state as a total system reset or the RESET instruction. Reset bits may be
found in the CP (in the CR), the IDMA (in the CMR), timer 1 (in the TMR1), and timer 2 (in
the TMR2).
When this bidirectional, open-drain signal is driven by an external device, it will cause the
IMP bus master (M68000 core, SDMA, or IDMA) to stop at the completion of the current
bus cycle. If the processor has stopped executing instructions due to a double-fault con-
dition, this line is driven by the processor to indicate to external devices that the processor
has stopped. An example of a double-fault condition is the occurrence of a bus error fol-
lowed by a second bus error during the bus error exception stacking process. This signal
is asserted with the RESET signal to cause a total MC68302 system reset. If BERR is as-
serted with the HALT signal, a retry cycle is performed.
This bidirectional, open-drain signal informs the bus master (M68000 core, SDMA, IDMA,
or external bus master) that there is a problem with the cycle currently being executed.
This signal can be asserted by the on-chip hardware watchdog (bus timeout because of
no DTACK), by the chip-select logic (address conflict or write-protect violation), or by ex-
ternal circuitry. If BERR is asserted with the HALT signal, a retry cycle is performed.
This input defines the M68000 processor mode (MC68000 or MC68008) and the data bus
width (16 bits or 8 bits, respectively). BUSW may only be changed upon a total system
reset. In 16-bit mode, all accesses to internal and external memory by the MC68000 core,
the IDMA, SDMA, and external master may be 16 bits, according to the assertion of the
UDS and LDS pins. In 8-bit mode, all M68000 core and IDMA accesses to internal and
external memory are limited to 8 bits. Also in 8-bit mode, SDMA accesses to external
memory are limited to 8 bits, but CP accesses to the CP side of the dual-port RAM con-
tinue to be 16 bits. In 8-bit mode, external accesses to internal memory are also limited to
8 bits at a time.
The MC68302 can be configured to work solely with an external CPU. In this mode the
on-chip M68000 core CPU should be disabled by asserting the DISCPU pin high during
a total system reset (RESET and HALT asserted). DISCPU may only be changed upon a
total system reset.
The DISCPU pin, for instance, allows use of several IMPs to provide more than three SCC
channels without the need for bus isolation techniques. Only one of the IMP M68000
cores is active and services the other IMPs as peripherals (with their respective cores dis-
abled). Refer to 3.8.4 Disable CPU Logic (M68000) for more details.
Low = 8-bit data bus, MC68008 core processor
High = 16-bit data bus, MC68000 core processor
MC68302 USER’S MANUAL
MOTOROLA