MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 227

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Reception Errors:
MOTOROLA
2. Clear-To-Send Lost (Collision) During Message Transmission. When this error occurs
1. Carrier Detect Lost During Message Reception. When this error occurs and the chan-
2. Overrun Error. The DDCMP controller maintains an internal three-byte FIFO for re-
3. CRC1 (Header CRC) Error. When this error occurs, the channel writes the received
4. CRC2 (Data or Maintenance CRC) or CRC3 (Control Message) Error. When this error
5. Framing Error. A framing error is detected by the DDCMP controller when no stop bit
and the channel is not programmed to control this line with software, the channel ter-
minates buffer transmission, closes the buffer, sets the CTS lost (CT) bit in the BD,
and generates the transmit error (TXE) interrupt (if enabled). The channel resumes
transmission after the reception of the RESTART TRANSMIT command.
nel is not programmed to control this line with software, the channel terminates mes-
sage reception, closes the buffer, sets the carrier detect lost (CD) bit in the BD, and
generates the receive block (RBK) interrupt (if enabled). This error has the highest pri-
ority. The rest of the message is lost, and other errors in that message are not
checked.
The channel will enter hunt mode immediately. It is possible that a SYN1–SYN2-
(SOH,DLE,ENQ) sequence in data will be incorrectly interpreted as the start of the
next header, but this "header" will have a CRC error.
ceiving data. The CP begins programming the SDMA channel (if the data buffer is in
external memory) and updating the CRC when the first word is received into the FIFO.
If the receive FIFO overrun error occurs, the channel writes the received data byte to
the internal FIFO on top of the previously received byte. The previous data byte is lost.
Then the channel closes the buffer, sets the overrun (OV) bit in the BD, and generates
the receive block (RBK) interrupt (if enabled).
The channel will enter hunt mode immediately. It is possible that a SYN1–SYN2-
(SOH,DLE,ENQ) sequence in data will be incorrectly interpreted as the start of the
next header, but this “header” will have a CRC error.
CRC to the data buffer, closes the buffer, sets the CRC error (CR) bit in the BD, gen-
erates the RBK interrupt (if enabled), increments the error counter (CRC1EC), and en-
ters hunt mode.
When this error occurs on data-and maintenance-message header fields, the channel
will enter hunt mode immediately. It is possible that a SYN1–SYN2-(SOH,DLE,ENQ)
sequence in data will be incorrectly interpreted as the start of the next header, but this
“header” will have a CRC error.
occurs, the channel writes the received CRC to the data buffer, closes the buffer, sets
the CRC error (CR) bit in the BD, and generates the RBK interrupt (if enabled). The
channel also increments the CRC2EC counter and enters hunt mode.
is detected in a received data string. When this error occurs, the channel writes the
received character to the buffer, closes the buffer, sets the framing error (FR) bit in the
BD, and generates the RBK interrupt (if enabled). When this error occurs, parity is not
checked for this character.
This error can occur only on synchronous links.
MC68302 USER’S MANUAL
NOTE
Communications Processor (CP)
4-107