MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 151
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
ENR—Enable Receiver
ENT—Enable Transmitter
MODE1–MODE0—Channel Mode
4.5.4 SCC Data Synchronization Register (DSR)
Each DSR is a 16-bit, memory-mapped, read-write register. DSR specifies the pattern used
in the frame synchronization procedure of the SCC in the synchronous protocols. In the
UART protocol it is used to configure fractional stop bit transmission. After reset, the DSR
defaults to $7E7E (two FLAGs); thus, no additional programming is necessary for the HDLC
protocol. For BISYNC, DDCMP, and V.110, the contents of the DSR should be written be-
fore the channel is enabled. Note that for the DDCMP, SYN1 must equal SYN2 must equal
DSYN1 for proper operation.
MOTOROLA
When ENR is set, the receiver is enabled. When it is cleared, the receiver is disabled, and
any data in the receive FIFO is lost. If ENR is cleared during data reception, the receiver
aborts the current character. ENR may be set or cleared regardless of whether serial
clocks are present. To restart reception, the ENTER HUNT MODE command should be
issued before ENR is set again.
When ENT is set, the transmitter is enabled; when ENT is cleared, the transmitter is dis-
abled. If ENT is cleared, the transmitter will abort any data transmission, clear the transmit
data FIFO and shift register, and force the TXD line high (idle). Data already in the trans-
mit shift register will not be transmitted. ENT may be set or cleared regardless of whether
serial clocks are present.
The STOP TRANSMIT command additionally aborts the current frame and would normal-
ly be given to the channel before clearing ENT. The command does not clear ENT auto-
matically. In a similar manner, to restart transmission, the user should issue the
RESTART TRANSMIT command and then set ENT. The command register is described
in 4.3 Command Set. The specific actions taken with each command vary somewhat ac-
cording to protocol and are discussed in each protocol section.
15
00 = HDLC
01 = Asynchronous (UART and DDCMP)
10 = Synchronous DDCMP and V.110
11 = BISYNC and Promiscuous Transparent
tools are 1) the ready bit in the transmit buffer descriptor, 2) the
ENT bit, 3) the STOP TRANSMIT command, 4) the RESTART
TRANSMIT command, and 5) the FRZ bit in the SCM (UART
mode only).
The DSR register has no relationship to the RS-232 signal “data
set ready,” which is also abbreviated DSR.
SYN2
MC68302 USER’S MANUAL
NOTE
8
7
Communications Processor (CP)
SYN1
4-31
0
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