MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 236
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
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Communications Processor (CP)
4.5.15.1 Bit Rate Adaption of Synchronous Data Signaling Rates up to 19.2 kbps
The V.110 synchronous bit rate adaption block diagram within the terminal adaptor is shown
in Figure 4-38.
This function may be implemented with two SCCs, one of which is configured for V.110 op-
eration. Step 1 (RA1) rate adaption can be achieved using one SCC channel programmed
to promiscuous (totally transparent) mode (see 4.5.13 BISYNC Controller). This SCC will
transfer the data between the R interface and IMP memory. The M68000 core must be pro-
grammed to format the data in memory according to the V.110 protocol to create the V.110
80-bit frame. Another SCC is used to transfer the data between IMP memory and the S/T
interface. This SCC should be programmed for V.110 operation, which provides the conver-
sion of the data rate to 64 kbps. Data may be transmitted and received on 1, 2, or 4 bits of
an ISDN B channel as programmed in the SIMASK register.
4.5.15.2 Rate Adaption of 48- and 56-kbps User Rates to 64 kbps
This function may again be implemented with two SCCs; however, in this case, the SCC
connected to the B channel is programmed to promiscuous (totally transparent) mode rather
than for V.110 operation (see 4.5.9 SCC Transparent Mode). The M68000 core will need to
format the framing pattern in the 48-kbps conversion case. For the 56-kbps rate conversion,
however, the B channel mask (SIMASK) in the serial channel physical interface can be
used.
4-116
V-SERIES
R
V.110 contains a requirement (under further study) for control in-
formation on the R interface (i.e., RTS, CTS, CD, DTR, and
DSR), conveyed by the S bits in the V.110 frame, not to have a
different transmission delay than the user data conveyed by the
D8–D1 bits. This very time-critical aspect of the standard is not
supported by the IMP. In this case, provision would need to be
made by the user to guarantee correct sampling times for this in-
formation to correspond with the user data. The IMP, however,
can detect changes in these signals and issue appropriate inter-
rupts to the M68000 core, allowing the function to be fully imple-
mented in a slightly longer time period.
Figure 4-38. Two-Step Synchronous Bit Rate Adaption
STEP 1
RA1
V
(2**k)*8
MC68302 USER’S MANUAL
kbps
NOTE
(2**k)*8
kbps
STEP 2
RA2
kbps
64
S/T
MOTOROLA
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