MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 277

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.11 PHYSICAL LAYER SERIAL INTERFACE PINS
The physical layer serial interface has 24 pins, and all but one of them have multiple func-
tionality. The pins can be used in a variety of configurations in ISDN or non-ISDN environ-
ments. Table 5-3 shows the functionality of each group of pins and their internal connection
to the three SCC and one SCP controllers. The physical layer serial interface can be config-
ured for non-multiplexed operation (NMSI) or multiplexed operation that includes IDL, GCI,
and PCM highway modes. IDL and GCI are ISDN interfaces. When working in one of the
multiplexed modes, the NMSI1/ISDN physical interface can be connected to all three SCC
controllers.
MOTOROLA
***
## Applies to disable CPU mode only, otherwise N/A.
# Applies to disable CPU mode only. The internal signal IBCLR is used otherwise.
**
A23–A1, FC–FC0,
AS, UDS, LDS, R/W, RMC
BCLR
IAC
D15—D0 Read
D15—D0 Write
DTACK
BR
BG
BGACK
HALT
RESET
BERR
If DTACK is generated automatically (internally) by the chip-select logic, then it is an output. Otherwise, it is an
input.
the chip-select logic detects address conflict or write protect violation. BERR may be asserted by external logic in
all cases.
BERR is an open-drain output, and may be asserted by the IMP when the hardware watchdog is used or when
Signal Name
NOTE: Each one of the parallel I/O pins can be configured individually.
First Function
NMSI1 (8)
NMSI2 (8)
NMSI3 (5)
NMSI3 (3)
Table 5-3. Bus Signal Summary—IDMA and SDMA
Table 5-4. Serial Interface Pin Functions
I/O Open Drain
I/O Open Drain
I/O Open Drain
I/O Open Drain
Pin Type
SCC1 Controller
SCC2 Controller
SCC3 Controller
SCC3 Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Connected To
O
MC68302 USER’S MANUAL
Memory
Internal
Space
I/O
O ##
O
I #
O
O
O
O
O
I ##
I
I
***
IDMA Master
Second Function
Access To
ISDN Interface
PIO—Port A
PIO—Port A
SCP
External
Memory
Space
I/O
O ##
**
I #
O
O
O
O
I ##
I
I
I
***
SCC1/SCC2/SCC3
Memory
Connected To
SCP Controller
Internal
Space
Parallel I/O
Parallel I/O
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SDMA Master
Access To
Signal Description
External
Memory
Space
I/O
O ##
**
O
O
O
O
O
I ##
I
I
I
***
5-13