MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 88

IC MPU MULTI-PROTOCOL 132-PQFP

MC68302EH16C

Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor

Specifications of MC68302EH16C

Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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System Integration Block (SIB)
RST—Reset Timer
ICLK—Input Clock Source for the Timer
FRR—Free Run/Restart
ORI—Output Reference Interrupt Enable
OM—Output Mode
CE—Capture Edge and Enable Interrupt
PS—Prescaler Value
3.5.2.2 Timer Reference Registers (TRR1, TRR2)
Each TRR is a 16-bit register containing the reference value for the timeout. TRR1 and
TRR2 are memory-mapped read-write registers.
3-38
This bit performs a software reset of the timer identical to that of an external reset.
The prescaler is programmed to divide the clock input by values from 1 to 256. The value
00000000 divides the clock by 1; the value 11111111 divides the clock by 256. The res-
olution of the timer varies directly with the size of the prescaler. In order to make smaller
adjustments to the timer as needed, the prescaler should be as small as possible (see
3.5.2.6 General Purpose Timer Example).
0 = Reset timer (software reset), includes clearing the TMR, TRR, and TCN.
1 = Enable timer
00 = Stop count
01 = Master clock
10 = Master clock divided by 16. Note that this clock source is not synchronized to the
11 = Corresponding TIN pin, TIN1 or TIN2 (falling edge)
0 = Free run—timer count continues to increment after the reference value is reached.
1 = Restart—timer count is reset immediately after the reference value is reached.
0 = Disable interrupt for reference reached (does not affect interrupt on capture func-
1 = Enable interrupt upon reaching the reference value
0 = Active-low pulse for one CLKO clock cycle (60 ns at 16.67 MHz)
1 = Toggle output
00 = Capture function is disabled
01 = Capture on rising edge only and enable interrupt on capture event
10 = Capture on falling edge only and enable interrupt on capture event
11 = Capture on any edge and enable interrupt on capture event
tion)
timer; thus, successive timeouts may vary slightly in length.
After reset, the TOUT signal begins in a high state, but is not
available externally until the PBCNT register is configured for
this function.
MC68302 USER’S MANUAL
NOTE
MOTOROLA

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