MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 237

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.5.15.3 Adaption for Asynchronous Rates up to 19.2 kbps
The V.110 asynchronous bit rate adaption block diagram within the terminal adaptor is
shown in Figure 4-39.
This function may be implemented in two SCCs. One SCC operates as a UART; the other
SCC operates as a V.110 controller. The M68000 core formats the data for transmission by
the V.110 at the 64 kbps data rate. Thus, the RA1 step is hidden in software.
4.5.15.4 V.110 Controller Overview.
By the appropriate setting of its SCC mode register, any of the SCC channels may be con-
figured to function as a V.110 controller. MODE1–MODE0 bits the SCC mode register
should be programmed to DDCMP, and the V.110 bit in the DDCMP mode register should
be set. The V.110 controller has the ability to receive and transmit V.110 80-bit frames. The
processing of those frames is handled by the M68000 core in software.
The V.110 receiver will synchronize on the 17-bit alignment pattern of the frame:
After achieving frame synchronization, the receiver will transfer the frame data to a receive
buffer (the leading one will be the MSB so that the programmer does not have to swap the
bits). The V.110 controller will write nine bytes of data to the buffer (discarding the first byte
of all zeros). The M68000 core should unformat the data in memory according to the V.110
protocol to create the data buffer; it may then use another SCC controller to transmit this
data to the R interface.
The V.110 transmitter will transmit a data buffer transparently with a bit swap (the MSB will
be transmitted first) onto a B channel. The data buffer should contain the 17-bit alignment
pattern. Another SCC controller may be used to receive data from the R interface. The
M68000 core should then format the data according to the V.110 protocol to create the
V.110 80-bit frame data buffer. The V.110 controller will then transmit it onto the B channel.
MOTOROLA
00000000
1xxxxxxx
V-SERIES
R
Figure 4-39. Three-Step Asynchronous Bit Rate Adaption
MANIPULATION
1xxxxxxx
1xxxxxxx
STOP-BIT
STEP 1
RA0
MC68302 USER’S MANUAL
1xxxxxxx
1xxxxxxx
(2**n)*600
bps
STEP 2
RA1
(2**k)*8
kbps
1xxxxxxx
1xxxxxxx
Communications Processor (CP)
1xxxxxxx
1xxxxxxx
(2**k)*8
kbps
STEP 3
RA2
kbps
64
S/T
4-117