MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 155

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Certain parameter RAM values need to be initialized by the user before the SCC is enabled.
Those values not so designated are initialized/written by the CP. Once initialized, most pa-
rameter RAM values will not need to be accessed in user software since most of the activity
is centered around the transmit and receive buffer descriptors, not the parameter RAM.
However, if the parameter RAM is accessed by the user, the following should be noted. The
parameter RAM can be read at any time. The parameter RAM values related to the SCC
transmitted can only be written 1) whenever the ENT bit in the SCM is zero or 2) after a
STOP TRANSMIT command and before a RESTART TRANSMIT command. The parame-
ter RAM values related to the SCC receiver can only be written 1) whenever the ENR bit in
the SCM is zero or 2) if the receiver has previously been enabled, after the ENTER HUNT
MODE command and before the ENR bit is set. See 4.5.10 Disabling the SCCs for a dis-
cussion of when the SCC registers may be changed.
The registers (see Table 4-6) that typically need to be accessed by the user are described
in the following paragraphs.
4.5.6.1 Data Buffer Function Code Register (TFCR, RFCR)
This register defines the address space of the receive (RFCR) and transmit (TFCR) data
buffers. These registers must be initialized if the SCC is used.
MOTOROLA
# Initialized by the user (M68000 core).
## Modified by the CP following a CP or system reset.
SCC Base + 80 #
SCC Base + 81 #
SCC Base + 82 #
SCC Base + 84 ##
SCC Base + 86 ##
SCC Base + 87 ##
SCC Base + 88
SCC Base + 8C
SCC Base + 8E
SCC Base + 90 ##
SCC Base + 92 ##
SCC Base + 93 ##
SCC Base + 94
SCC Base + 98
SCC Base + 9A
SCC Base + 9C
SCC Base + BF
Address
The value of the function code register for any channel may be
equal to that of any other, but do not initialize FC2–FC0 with the
value “111” which causes a conflict with the interrupt acknowl-
edge cycle to occur.
Table 4-6. SCC Parameter RAM Memory Map
7
0
MRBLR
Name
RFCR
TFCR
RBD#
TBD#
FC2
6
MC68302 USER’S MANUAL
FC1
5
FC0
4
NOTE
2 Words
2 Words
Width
Word
Word
Word
Word
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
3
0
2
0
Rx Function Code
Tx Function Code
Maximum Rx Buffer Length
Rx Internal State
Reserved
Rx Internal Buffer Number
Rx Internal Data Pointer
Rx Internal Byte Count
Rx Temp
Tx Internal State
Reserved
Tx Internal Buffer Number
Tx Internal Data Pointer
Tx Internal Byte Count
Tx Temp
First Word of Protocol-Specific Area
Last Word of Protocol-Specific Area
1
0
Communications Processor (CP)
0
0
Description
4-35