MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 199

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The first word of the Tx BD contains status and control bits. Bits 15–10 are prepared by the
user before transmission; bits 1–0 are set by the HDLC controller after the buffer has been
transmitted. Bit 15 is set by the user when the buffer and BD have been prepared and is
cleared by the HDLC controller after the frame has been transmitted.
R—Ready
X—External Buffer
W—Wrap (Final BD in Table)
I—Interrupt
L—Last
TC—Tx CRC
Bits 9–2—Reserved for future use.
The following status bits are written by the HDLC controller after it has finished transmitting
the associated data buffer.
MOTOROLA
This bit is valid only when the last (L) bit is set.
0 = This buffer is not currently ready for transmission. The user is free to manipulate
1 = The data buffer, which has been prepared for transmission by the user, has not yet
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the HDLC
0 = No interrupt is generated after this buffer has been serviced.
1 = Either TXB or TXE in the HDLC event register will be set when this buffer has been
0 = This is not the last buffer in the frame.
1 = This is the last buffer in the current frame.
0 = Transmit the closing flag after the last data byte. This setting can be used for test-
1 = Transmit the CRC sequence after the last data byte.
this BD (or its associated buffer). The HDLC controller clears this bit after the buffer
has been fully transmitted or after an error condition has been encountered.
transmitted. No fields of this BD may be written by the user once this bit is set.
controller will transmit data from the first BD in the table.
serviced by the HDLC controller, which can cause an interrupt.
ing purposes to send a “bad” CRC after the data.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
MC68302 USER’S MANUAL
NOTE
Communications Processor (CP)
4-79