MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 402

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
D.8.5 Transparent Mode with the NMSI Physical Interface
NMSI has two independent data signals, TXD and RXD, and two independent clocking sig-
nals, TCLK and RCLK. TCLK and RCLK may be individually chosen to be generated inter-
nally or externally to the MC68302.
NMSI also has three control signals: RTS, CTS, and CD. First, let's discuss their properties
in general. The SCC forces RTS low when it is ready to transmit data, but the SCC waits
until it sees CTS is low before doing this. After the frame has been transmitted, the RTS sig-
nal is negated (high). The CTS signal should stay low during the entire time RTS is low, or
transmission is aborted and a CTS lost error is indicated in the transmit buffer descriptor (Tx
BD). On the receiving side, the CD signal going low tells the MC68302 to gate data into this
SCC. Once low, CD should remain low for the entire frame, or reception is terminated and
a CD lost error is signaled in the receive buffer descriptor (Rx BD).
Sometimes the CTS and CD input functions described above are not appropriate for an ap-
plication. In this case, the software operation mode in the SCC mode register (SCM) can be
chosen by programming the DIAG1-DIAG0 bits. In the software operation mode, as far as
the SCC is concerned, CTS and CD are always low. However, the real value of the CTS and
CD lines externally can be read in the SCCS register once the transmitter and receiver are
enabled, and changes in these lines can generate interrupts via the SCCE register. Software
operation mode does not affect RTS because, since RTS is an output, RTS can always be
ignored by the external logic.
In totally transparent mode (and also BISYNC mode), the CD signal can become a synchro-
nization input. When discussing the CD signal during totally transparent mode in this docu-
ment, CD will be referred to as “CD (sync)”. The totally transparent mode is initiated by
setting the EXSYN bit in the SCM. With EXSYN set, a high-to-low transition on CD (sync)
defines the start of both transmission and reception of transparent mode frames. Subse-
quent high and low transitions of CD (sync) have no effect on the reception of data. The only
way to reinitiate the SYNC process is to issue an ENTER HUNT MODE command to the
channel, and then force another high-to-low transition on CD (sync).
Figure D-23 shows the simplest NMSI transmit case. NTSYN and EXSYN are set to enable
transparent mode, and the L bit is set. Software operation mode (DIAG1 = 1 and DIAG0 =
1) is chosen to eliminate using CTS to control transmission. However, since EXSYN = 1, CD
becomes CD (sync), and transmission cannot begin until CD (sync) is low (which can be ac-
complished by grounding CD (sync)). Thus, there will only be a 1-bit delay between RTS be-
ing asserted by the transmitter and actual data being transmitted. Since the L bit is set, RTS
is negated after the last byte in the frame.
In the preceding example, if multiple buffers had been ready with their L bits cleared, RTS
would have remained asserted, and the next buffer's data would have begun immediately.
If multiple buffers had been ready with their L bits set, RTS would have been asserted again
after a delay of at least 17 idle bits on the line (the exact number of bits is load dependent).
D-52
MC68302 USER’S MANUAL
MOTOROLA