MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 43

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

try is $0F0; however, the actual BAR is a 16-bit value within the BAR entry and is located at
$0F2.
After a total system reset, the on-chip peripheral base address is undefined, and it is not
possible to access the on-chip peripherals at any address until BAR is written. The BAR and
the SCR can always be accessed at their fixed addresses.
Do not assign other devices on the system bus an address that falls within the address
range of the peripherals defined by the BAR. If this happens, BERR is generated (if the ad-
dress decode conflict enable (ADCE) bit is set) and the address decode conflict (ADC) bit in
the SCR is set.
The BAR is a 16-bit, memory-mapped, read-write register consisting of the high address
bits, the compare function code bit, and the function code bits. Upon a total system reset, its
value may be read as $BFFF, but its value is not valid until written by the user. The address
of this register is fixed at $0F2 in supervisor data space. BAR cannot be accessed in user
data space.
Bits 15–13—FC2–FC0
MOTOROLA
15
The FC2–FC0 field is contained in bits 15–13 of the BAR. These bits are used to set the
address space of 4K-byte block of on-chip peripherals. The address compare logic uses
these bits, dependent upon the CFC bit, to cause an address match within its address
space.
FC2–FC0
13
The BAR, SCR and CKCR registers are internally reset only
when a total system reset occurs by the simultaneous assertion
of RESET and HALT. The chip-select (CS) lines are not assert-
ed on accesses to these locations. Thus, it is very helpful to use
CS lines to select external ROM/RAM that overlaps the BAR and
SCR register locations, since this prevents potential bus conten-
tion. (The internal access (IAC) signal may also be used to pre-
vent bus contention.)
In 8-bit system bus operation, IMP accesses are not possible un-
til the low byte of the BAR is written. Since the MOVE.W instruc-
tion writes the high byte followed by the low byte, this instruction
guarantees the entire word is written.
Do not assign this field to the M68000 core interrupt acknowl-
edge space (FC2–FC0 = 7).
CFC
12
11
23
22
MC68302 USER’S MANUAL
21
20
NOTE
NOTE
NOTE
19
BASE ADDRESS
18
17
16
MC68000/MC68008 Core
15
14
13
2-13
12
0