MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 250

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

OFFSET + 0
OFFSET + 2
OFFSET + 4
Communications Processor (CP)
Bits 11–6—Reserved for future use; should be written with zero.
COMMON SCC MODE BITS—See 4.5.3 SCC Mode Register (SCM) for a description of the
DIAG1, DIAG0, ENR, ENT, MODE1, and MODE0 bits.
4.5.16.8 Transparent Receive Buffer Descriptor (RxBD)
The CP reports information about the received data for each buffer using BD. The Rx BD is
shown in Figure 4-42. The CP closes the current buffer, generates a maskable interrupt, and
starts to receive data into the next buffer after one of the following events:
OFFSET +6
The first word of the Rx BD contains control and status bits.
E—Empty
X—External Buffer
W—Wrap (Final BD in Table)
4-130
• Detecting an error
• Detecting a full receive buffer
• Issuing the ENTER HUNT MODE command
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with this BD is empty. This bit signifies that the BD and
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of this BD.
its associated buffer are available to the CP. After it sets this bit, the M68000 core
should not write to any fields of this BD when this bit is set. The empty bit will re-
main set while the CP is currently filling the buffer with received data.
receive incoming data into the first BD in the table. Setting this bit allows the use
of fewer than eight BDs to conserve internal RAM.
15
E
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
14
X
Figure 4-42. Transparent Receive Buffer Descriptor
13
W
12
I
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
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MC68302 USER’S MANUAL
10
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NOTE
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9
DATA LENGTH
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8
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7
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6
—
5
—
4
—
3
—
2
MOTOROLA
OV
1
CD
0