MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 234

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
Data Length
Tx Buffer Pointer
4.5.14.12 DDCMP Event Register
The SCC event register (SCCE) is referred to as the DDCMP event register when the SCC
is configured for DDCMP. It is an 8-bit register used to report events recognized by the DDC-
MP channel and to generate interrupts. On recognition of an event, the DDCMP controller
sets its corresponding bit in this register. Interrupts generated by this register may be
masked in the DDCMP mask register.
The DDCMP event register is a memory-mapped register that may be read at any time. A
bit is cleared by writing a one (writing zero does not affect a bit's value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
Bit 5—Reserved for future use.
TXE—Tx Error
RBK—Receive Block
BSY—Busy Condition
4-114
The data length is the number of octets that the DDCMP controller should transmit from
this BD's data buffer. It is never modified by the CP. The data length should be greater
than zero.
This pointer, which contains the address of the associated data buffer, may be even or
odd. The buffer may reside in either internal or external memory.
A change in the status of the CTS line was detected on the DDCMP channel. The SCC
status register may be read to determine the current status.
A change in the status of the CD line was detected on the DDCMP channel. The SCC sta-
tus register may be read to determine the current status.
An error (CTS lost or underrun) occurred on the transmitter channel.
A complete block has been received on the DDCMP channel. A block is defined as recep-
tion of a complete header, a complete message, or a receiver error condition.
A data byte was received and discarded due to lack of buffers. The receiver will enter hunt
mode automatically.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
CTS
7
CD
6
MC68302 USER’S MANUAL
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5
TXE
NOTE
4
RBK
3
BSY
2
TX
1
RBD
0
MOTOROLA