MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 249

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.5.16.7 Transparent Mode Register
Each SCC mode register is a 16-bit, memory-mapped, read-write register that controls the
SCC operation. The term transparent mode register refers to the protocol-specific bits (15–
6) of the SCC mode register when that SCC is configured for transparent mode. The trans-
parent mode register is cleared by reset. All undefined bits should be written with zero.
Bit 15—Reserved for future use; should be written with zero.
EXSYN — External Sync Mode
NTSYN—No Transmit SYNC
REVD—Reverse Data
MOTOROLA
2. Carrier Detect Lost During Message Reception—When this error occurs and the chan-
3. Busy Condition—If the RISC controller tries to use an Rx BD that is not empty, the
When this mode is selected, the receiver and transmitter expect external logic to indicate
the beginning of the data field by using the CD1/L1SY1 pin, if SCC1 is used, and the CD2
and CD3 pins, respectively, if SCC2 or SCC3 is used. In this mode, there is no carrier de-
tect function for the SCC.
When the channel is programmed to work through the serial channels physical interface
(IDL or GCI) and EXSYN is set, the layer 1 logic carries out the synchronization using the
L1SY1 pin. In PCM mode, the L1SY1–L1SY0 pins are used. In NMSI mode, the CD pins
(and the CD timing) are used to synchronize the data. CD should go low on the second
valid data bit of the receive data stream.
If this bit is cleared, the receiver will look for the SYN1–SYN2 sequence in the data syn-
chronization register to achieve synchronization, and the transmitter uses the CTS pin ac-
cording to the DIAG1–DIAG0 bits in the SCM. The receiver also uses the CD pin
according to the DIAG1–DIAG0 bits in the SCM.
This bit must be set for the SCC to operate in a totally transparent (promiscuous) mode.
When this bit is set, the receiver and transmitter will reverse the character bit order, trans-
mitting the most significant bit first.
15
—
the buffer, sets the overrun (OV) bit in the BD, and generates the RX interrupt (if en-
abled). The receiver then enters hunt mode immediately.
nel is not programmed to control this line with software, the channel terminates recep-
tion, closes the buffer, sets the carrier detect lost (CD) bit in the BD, and generates the
RX interrupt (if enabled). This error has the highest priority; the rest of the message is
lost and no other errors are checked. The receiver then enters hunt mode immediately.
busy condition is encountered. No data is received and the current Rx BD is left un-
modified. After new buffers are provided, the user should issue the ENTER HUNT
MODE command.
EXSYN
14
NTSYN
13
REVD
12
11
—
MC68302 USER’S MANUAL
10
—
—
9
—
8
7
—
Communications Processor (CP)
6
—
5
COMMON SCC MODE BITS
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