MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 178

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

OFFSET + 0
OFFSET + 2
OFFSET + 4
Communications Processor (CP)
OFFSET +6
The first word of the Rx BD contains the control and status bits.
An example of the UART receive process is shown in Figure 4-21. This figure shows the re-
sulting state of the Rx BDs after receipt of 10 characters, an idle period, and five charac-
ters—one with a framing error. The example assumes that MRBLR = 8 in the SCC
parameter RAM.
E—Empty
X—External Buffer
W—Wrap (Final BD in Table)
4-58
5. Reception of an address character when working in multidrop mode
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with the BD is empty. This bit is used to signify that the
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of the BD.
BD and its associated buffer are available to the CP. After it sets this bit, the
M68000 core should not write to any fields of this BD when this bit is set. Note that
the empty bit will remain set while the CP is currently filling the buffer with received
data.
receive incoming data into the first BD in the table, allowing the user to use fewer
than eight BDs to conserve internal RAM.
15
E
In the nonautomatic multidrop mode (UM1–UM0 = 01), the ad-
dress character will be written into the next buffer for comparison
by the user software.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
14
X
Figure 4-20. UART Receive Buffer Descriptor
13
W
12
I
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
C
MC68302 USER’S MANUAL
10
A
NOTE
NOTE
M
9
DATA LENGTH
ID
8
—
7
—
6
BR
5
FR
4
PR
3
—
2
MOTOROLA
OV
1
CD
0