MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 190

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
The HDLC controller uses the same data structure as the UART, BISYNC, and DDCMP con-
trollers. This data structure supports multibuffer operation and address comparisons.
The receive errors (overrun, nonoctet aligned frame, CD lost, aborted frame, and CRC error)
are reported through the receive BD. The transmit errors (underrun and CTS lost) are re-
ported through the transmit BD. An indication about the status of the lines (idle, CD, and
CTS) is reported through the SCC status register (SCCS), and a maskable interrupt is gen-
erated upon a status change in any one of those lines.
4.5.12.5 HDLC Command Set
The following commands are issued to the command register.
STOP TRANSMIT Command
RESTART TRANSMIT Command
4-70
After a hardware or software reset and the enabling of the channel in the SCC mode reg-
ister, the channel is in the transmit enable mode and starts polling the first BD in the table
approximately every eight or sixteen transmit clocks as determined by the FLG bit in the
HDLC mode register.
The channel STOP TRANSMIT command disables the transmission of frames on the
transmit channel. If this command is received by the HDLC controller during frame trans-
mission, transmission of that frame is aborted after the contents of the FIFO are transmit-
ted (up to four words). The TBD# is not advanced. No new BD is accessed, and no new
frames are transmitted for this channel. The transmitter will transmit an abort sequence (if
the command was given during frame transmission) and then begin to transmit flags or
idles as indicated by the HDLC mode register. The abort sequence on transmit is a zero
followed by seven ones (01111111).
This command is useful for performing frame retransmission. The M68000 core may issue
the STOP TRANSMIT command, reorganize the transmit BD table, and issue the RE-
START TRANSMIT command. The STOP TRANSMIT command may also be used in the
X.25 protocol to send a reject frame or a link reset command.
The STOP TRANSMIT command must be issued before the SCC mode register is used
to disable the transmitter if the transmitter is to be re-enabled at a later time.
The RESTART TRANSMIT command re-enables the transmission of characters on the
transmit channel. This command is expected by the HDLC controller after a STOP
TRANSMIT command, after a STOP TRANSMIT command and disabling the channel in
its SCC mode register, or after transmitter error (underrun or CTS lost when no automatic
frame retransmission is performed). The HDLC controller will resume transmission from
the current transmitter BD (TBD#) in the channel's transmit BD table.
If the transmitter is being re-enabled, the RESTART TRANSMIT command must be used
and should be followed by the enabling of the transmitter in the SCC mode register.
MC68302 USER’S MANUAL
MOTOROLA