MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 285

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Each of these five pins can be used either as a dedicated timer function or as a general-
purpose port B I/O port pin. Note that the timers do not require the use of external pins. The
input buffers have Schmitt triggers.
TIN1/PB3—Timer 1 Input
This input is used as a timer clock source for timer 1 or as a trigger for the timer 1 capture
register. TIN1 may also be used as the external clock source for any or all three SCC baud
rate generators.
TOUT1/PB4—Timer 1 Output
This output is used as an active-low pulse timeout or an event overflow output (toggle) from
timer 1.
TIN2/PB5—Timer 2 Input
This input can be used as a timer clock source for timer 2 or as a trigger for the timer 2 cap-
ture register.
TOUT2/PB6—Timer 2 Output
This output is used as an active-low pulse timeout or as an event overflow output (toggle)
from timer 2.
WDOG/PB7—Watchdog Output
This active-low, open-drain output indicates expiration of the watchdog timer. WDOG is as-
serted for a period of 16 clock (CLKO) cycles and may be externally connected to the RE-
SET and HALT pins to reset the MC68302. WDOG is never asserted by the on-chip
hardware watchdog (see the BERR signal description). The WDOG pin function is enabled
after a total system reset. It may be reassigned as the PB7 I/O pin in the PBCNT register.
MOTOROLA
Figure 5-15. Timer Pins
MC68302 USER’S MANUAL
MC68302
TIN1 / PB3
TOUT1 / PB4
TIN2 / PB5
TOUT2 / PB6
WDOG / PB7
Signal Description
5-21