MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 100

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
EXTAL can also accept a CMOS-level clock input. The crystal output (XTAL) connects the
internal crystal generator output to an external crystal. If an external clock is used, XTAL
should be left unconnected. The CLKO pin, which drives the high-speed system clock, may
be used to synchronize other peripherals to the IMP system clock.
3.8 SYSTEM CONTROL
The IMP system control consists of a System Control Register (SCR) that configures the fol-
lowing functions:
3.8.1 System Control Register (SCR)
The SCR is a 32-bit register that consists of system status and control bits, a bus arbiter con-
trol bit, hardware watchdog control bits, low-power control bits, and freeze select bits. Refer
to Figure 3-11, Table 3-7, and to the following paragraphs for a description of each bit in this
register. The SCR is a memory-mapped read-write register. The address of this register is
fixed at $0F4 in supervisor data space (FC = 5).
3-50
• System Status and Control Logic
• AS Control During Read-Modify-Write-Cycles
• Disable CPU (M68000) Logic
• Bus Arbitration Logic with Low-Interrupt Latency Support
• Hardware Watchdog
• Low-Power (Standby) Modes
• Freeze Control
LPREC
FRZW
31
23
15
0
0
7
Figure 3-11. System Control Register
LPP16
ERRE
FRZ2
30
22
14
6
0
MC68302 USER’S MANUAL
FRZ1
LPEN
VGE
29
21
13
5
0
WPVE
SAM
28
20
12
0
4
RMCST
HWDEN
LOW-POWER CLOCK DIVIDER
IPA
27
19
11
EMWS
HWT
26
18
10
HWDCN2–HWDCN0
ADCE
WPV
25
17
BCLM
ADC
24
16
8
0
MOTOROLA