MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 67

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Steps 2 and 4 are the responsibility of the M68000 core on the IMP; whereas, steps 1 and
3 are the responsibility of the interrupt controller on the IMP.
The M68000 core is not modified on the IMP; thus, steps 2 and 4 operate exactly as they
would on the MC68000. In step 2, the M68000 status register (SR) is available to mask in-
terrupts globally or to determine which priority levels can currently generate interrupts (see
2.5 Interrupt Processing for more details). Also in step 2, the interrupt acknowledge cycle is
executed.
The interrupt acknowledge cycle carries out a standard M68000 bus read cycle, except that
FC2–FC0 are encoded as 111, A3–A1 are encoded with the interrupt priority level (1–7, with
7 (i.e., 111) being the highest), and A19–A16 are driven high. UDS and LDS are both driven
low.
In step 4, the M68000 reads the vector number, multiplies it by 4 to get the vector address,
fetches a 4-byte program address from that vector address (seeTable 2-5), and then jumps
to that 4-byte address. That 4-byte address is the location of the first instruction in the inter-
rupt handler.
Steps 1 and 3 are the responsibility of the interrupt controller on the IMP. In steps 1 and 3,
a number of configuration options are available. For instance, in step 1, there are two modes
for handling external interrupts: normal and dedicated. In step 3, there are several different
ways of generating vectors. These and other interrupt controller options are introduced in
the following paragraphs.
3.2.1.2 Interrupt Controller Overview
The interrupt controller receives interrupts from internal sources such as the timers, the
IDMA controller, the serial communication controllers, and the parallel I/O pins (port B pins
11–8). These interrupts are called internal requests (INRQ). The interrupt controller allows
for masking each INRQ interrupt source. When multiple events within a peripheral can
cause the INRQ interrupt, each event is also maskable in a register in that peripheral.
In addition to the INRQ interrupts, the interrupt controller can also receive external requests
(EXRQ). EXRQ interrupts are input to the IMP according to normal or dedicated mode. In
the normal mode, EXRQ interrupts are encoded on the IPL2–IPL0 lines. In the dedicated
mode, EXRQ interrupts are presented directly as IRQ7, IRQ6, and IRQ1.
Normal Mode
MOTOROLA
3. The interrupt controller recognizes the interrupt acknowledge cycle and places the in-
4. The M68000 reads the vector, reads the address of the interrupt handler in the excep-
In this mode, the three external interrupt request pins are configured as IPL2–IPL0 as in
the original MC68000. Up to seven levels of interrupt priority may be encoded. Level 4 is
reserved for IMP INRQ interrupts and may not be generated by an external device.
bus cycle after the completion of the current instruction.
terrupt vector for that interrupt request onto the M68000 bus.
tion vector table, and then begins execution at that address.
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-17