MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 436

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

SCC Programming Reference
E.1.2.3 SCC INITIALIZATION.
E.1.2.4 SCC OPERATION.
E.1.2.5 SCC INTERRUPT HANDLING.
E-14
5. Write MRBLR.
6. Write CRC_Mask_L and CRC_Mask_H.
7. Write DISFC.
8. Write CRCEC.
9. Write ABTSC.
10. Write NMARC.
11. Write RETRC.
12. Write MFLR.
13. Write HMASK.
14. Write HADDR1, HADDR2, HADDR3, and HADDR4.
15. Write SCON.
16. Write SCM without setting the ENR and ENT bits.
17. Write DSR.
18. Write SCCE with $FF to clear any previous events.
19. Write SCCM.
20. Write IMR.
21. Write the Rx buffer descriptor control/status, buffer pointer high, and buffer pointer
22. Prepare transmit buffers as required to transmit data on the SCC. Set the R bit in each
23. Write SCM, setting the ENR and ENT bits to enable reception and transmission on the
24. Prepare more transmit buffers as required to transmit data on the SCC.
1. Read the SCC event register.
2. Clear any unmasked bits that will be used in this interrupt routine.
3. Handle the interrupt events as required by the system.
4. Clear the appropriate SCC bit in the in-service register (ISR) of the interrupt
5. Return from the interrupt.
low words for all of the buffer descriptors that are going to be used. Set the W bit
in the last buffer descriptor to be used in the queue.
Tx buffer descriptor's control/status word when the data buffer is ready for transmis-
sion. Set the W bit in the last Tx buffer descriptor in the table so that the IMP will use
the first Tx buffer descriptor (after the user sets the R bit) for the next transmission.
SCC.
controller.
MC68360 USER’S MANUAL
MOTOROLA