MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet
MC68302EH16C
Specifications of MC68302EH16C
Available stocks
Related parts for MC68302EH16C
MC68302EH16C Summary of contents
Page 1
Microprocessors and Memory Technologies Group Integrated Multiprotocol Processor Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor ...
Page 2
MC68302 USER’S MANUAL MOTOROLA ...
Page 3
The complete documentation package for the MC68302 consists of the M68000PM/AD, MC68000 Family Programmer’s Reference Manual, MC68302UM/AD, MC68302 Integrated Multiprotocol Processor User’s Manual, and the MC68302/D, MC68302 Integrated Multipro- tocol Processor Product Brief . The MC68302 Integrated Multiprotocol Processor User’s ...
Page 4
ALABAMA , Huntsville ARIZONA , Tempe CALIFORNIA , Agoura Hills CALIFORNIA , Los Angeles CALIFORNIA , Irvine CALIFORNIA , Rosevllle CALIFORNIA , San Diego CALIFORNIA , Sunnyvale COLORADO , Colorado Springs COLORADO , Denver CONNECTICUT , Wallingford FLORIDA , Maitland ...
Page 5
TABLE OF CONTENTS Paragraph Number 1.1 Block Diagram......................................................................................... 1-1 1.2 Features .................................................................................................. 1-3 1.3 MC68302 System Architecture ............................................................... 1-4 1.4 NMSI Communications-Oriented Environment ....................................... 1-5 1.5 Basic Rate ISDN or Digital Voice/Data Terminal .................................... 1-6 2.1 Programming Model................................................................................ 2-1 2.2 ...
Page 6
Table of Contents Paragraph Number 3.1.4.3 Address Sequencing..............................................................................3-10 3.1.4.4 Transfer Request Generation ................................................................3-11 3.1.4.5 Block Transfer Termination....................................................................3-12 3.1.5 IDMA Programming ...............................................................................3-13 3.1.6 DMA Bus Arbitration ..............................................................................3-14 3.1.7 Bus Exceptions ......................................................................................3-14 3.1.7.1 Reset......................................................................................................3-15 3.1.7.2 Bus Error................................................................................................3-15 3.1.7.3 Halt.........................................................................................................3-15 3.1.7.4 Relinquish and ...
Page 7
Paragraph Number 3.5.3.1 Software Watchdog Timer Operation .................................................... 3-41 3.5.3.2 Software Watchdog Reference Register (WRR) ................................... 3-41 3.5.3.3 Software Watchdog Counter (WCN) ..................................................... 3-42 3.6 External Chip-Select Signals and Wait-State Logic .............................. 3-42 3.6.1 Chip-Select Logic Key Features............................................................ 3-45 3.6.2 ...
Page 8
Table of Contents Paragraph Number 4.4.5 Serial Interface Registers.......................................................................4-19 4.4.5.1 Serial Interface Mode Register (SIMODE).............................................4-19 4.4.5.2 Serial Interface Mask Register (SIMASK)..............................................4-22 4.5 Serial Communication Controllers (SCCs).............................................4-22 4.5.1 SCC Features ........................................................................................4-24 4.5.2 SCC Configuration Register (SCON).....................................................4-24 4.5.2.1 Asynchronous Baud Rate Generator ...
Page 9
Paragraph Number 4.5.12.1 HDLC Channel Frame Transmission Processing.................................. 4-68 4.5.12.2 HDLC Channel Frame Reception Processing....................................... 4-68 4.5.12.3 HDLC Memory Map............................................................................... 4-69 4.5.12.4 HDLC Programming Model ................................................................... 4-69 4.5.12.5 HDLC Command Set............................................................................. 4-70 4.5.12.6 HDLC Address Recognition .................................................................. 4-71 4.5.12.7 HDLC ...
Page 10
Table of Contents Paragraph Number 4.5.15.2 Rate Adaption of 48- and 56-kbps User Rates to 64 kbps...................4-116 4.5.15.3 Adaption for Asynchronous Rates up to 19.2 kbps..............................4-117 4.5.15.4 V.110 Controller Overview. ..................................................................4-117 4.5.15.5 V.110 Programming Model ..................................................................4-118 4.5.15.6 Error-Handling Procedure ....................................................................4-118 ...
Page 11
Paragraph Number 5.6 Data Bus Pins (D15—D0) ....................................................................... 5-7 5.7 Bus Control Pins...................................................................................... 5-8 5.8 Bus Arbitration Pins............................................................................... 5-10 5.9 Interrupt Control Pins ............................................................................ 5-11 5.10 MC68302 Bus Interface Signal Summary ............................................. 5-12 5.11 Physical Layer Serial Interface Pins...................................................... 5-13 ...
Page 12
Table of Contents Paragraph Number Mechanical Data and Ordering Information 7.1 Pin Assignments ......................................................................................7-1 7.1.1 Pin Grid Array (PGA) ...............................................................................7-1 7.1.2 Plastic Surface Mount (PQFP).................................................................7-2 7.1.3 Thin Surface Mount (TQFP).....................................................................7-3 7.2 Package Dimensions ...............................................................................7-4 7.2.1 Pin Grid Array (PGA) ...............................................................................7-4 ...
Page 13
Paragraph Number D.3.2 MC68302 Buffer Processing ...................................................................D-8 D.3.3 New Pointers ...........................................................................................D-9 D.3.4 Initial Conditions ....................................................................................D-10 D.3.5 Transmit Algorithm ................................................................................D-10 D.3.6 Interrupt Routine....................................................................................D-10 D.3.7 Final Comments ....................................................................................D-11 D.3.8 HDLC Code Listing................................................................................D-11 D.4 Configuring A Uart on the MC68302 .....................................................D-17 D.4.1 Purpose ...
Page 14
Table of Contents Paragraph Number D.7.6 Final Notes............................................................................................ D-45 D.8 Using the MC68302 Transparent Mode................................................ D-45 D.8.1 Transparent Mode Definition................................................................. D-45 D.8.2 Applications for Transparent Mode ....................................................... D-46 D.8.3 Physical Interface to Accompany Transparent Mode ........................... D-47 D.8.4 General Transparent ...
Page 15
Paragraph Number E.1.1.3.6 ABTSC—Abort Sequence Counter. ......................................................E-10 E.1.1.3.7 NMARC—Nonmatching Address Received Counter. ........................... E-10 E.1.1.3.8 RETRC—Frame Retransmission Counter. ........................................... E-10 E.1.1.3.9 MFLR—Maximum Frame Length Register............................................E-10 E.1.1.3.10 HMASK—HDLC Frame Address Mask ................................................. E-10 E.1.1.3.11 HADDR1, HADDR2, HADDR3, and HADDR4-HDLC Frame Address..E-10 ...
Page 16
Table of Contents Paragraph Number E.2.1.4.2 Receive Buffer Data Length.................................................................. E-27 E.2.1.4.3 Receive Buffer Pointer. ......................................................................... E-27 E.2.1.5 Transmit Buffer Descriptors. ................................................................. E-27 E.2.1.5.1 Transmit BD Control/Status Word......................................................... E-27 E.2.1.5.2 Transmit Buffer Data Length................................................................. E-28 E.2.2 Programming the SCC for ...
Page 17
Figure Number Figure 1-1. MC68302 Block Diagram ........................................................................... 1-2 Figure 1-2. General-Purpose Microprocessor System Design ..................................... 1-4 Figure 1-3. MC68302 System Design........................................................................... 1-5 Figure 1-4. NMSI Communications-Oriented Board Design......................................... 1-7 Figure 1-5. Basic Rate IDL Voice/Data Terminal in ISDN ............................................ ...
Page 18
Table of Contents Figure Number Figure 4-5. Serial Channels Physical Interface Block Diagram .................................. 4-10 Figure 4-6. IDL Bus Signals ....................................................................................... 4-11 Figure 4-7. IDL Terminal Adaptor ............................................................................... 4-12 Figure 4-8. GCI Bus Signals....................................................................................... 4-15 Figure 4-9. Two PCM Sync ...
Page 19
Figure Number Figure 5-2. Clock Pins .................................................................................................. 5-4 Figure 5-3. System Control Pins................................................................................... 5-5 Figure 5-4. Address Bus Pins ....................................................................................... 5-7 Figure 5-5. Data Bus Pins............................................................................................. 5-7 Figure 5-6. Bus Control Pins......................................................................................... 5-8 Figure 5-7. External Address/Data Buffer..................................................................... 5-9 Figure ...
Page 20
Table of Contents Figure Number Development Tools and Support Figure B-1. Software Overview .....................................................................................B-3 Figure B-2. MC68302FADS ..........................................................................................B-8 Figure C-1. CP Architecture Running RAM Microcode .................................................C-1 Figure D-1. MC68302 Minimum System Configuration (Sheet 1 of 2)..........................D-2 Figure D-2. MC68302 Minimum ...
Page 21
Table Number Table 2-1. M68000 Data Addressing Modes .................................................................2-4 Table 2-2. M68000 Instruction Set Summary.................................................................2-5 Table 2-3. M68000 Instruction Type Variations .............................................................2-6 Table 2-4. M68000 Address Spaces..............................................................................2-7 Table 2-5. M68000 Exception Vector Assignment .........................................................2-8 Table 2-6. System Configuration Register ...................................................................2-14 ...
Page 22
Table of Contents Table Number Table 5-1. Signal Definitions .......................................................................................... 5-1 Table 5-2. Bus Signal Summary—Core and External Master...................................... 5-12 Table 5-3. Bus Signal Summary—IDMA and SDMA ................................................... 5-13 Table 5-4. Serial Interface Pin Functions..................................................................... 5-13 Table 5-5. Typical ISDN ...
Page 23
SECTION 1 GENERAL DESCRIPTION The MC68302 integrated multiprotocol processor (IMP very large-scale integration (VL- SI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications ...
Page 24
General Description M68000 BUS INTERRUPT CONTROLLER 1 CHANNEL IDMA DRAM REFRESH CONTROLLER 6 CHANNELS SDMA MAIN CONTROLLER (RISC) Figure 1-1. MC68302 Block Diagram 1-2 MC68000/MC68008 CORE ON-CHIP PERIPHERALS BUS INTERFACE UNIT 1152 BYTES BUS ARBITER DUAL-PORT STATIC RAM 3 TIMERS ...
Page 25
The MC68302 can also be used in applications such as board-level industrial controllers performing real-time control applications with a local control bus and an X.25 packet network connection. Such a system provides the real-time response to a demanding peripheral while ...
Page 26
General Description Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals —SCP for Synchronous Communication —Two Serial Management Controllers (SMCs) To Support IDL and GCI Auxiliary Channels 1.3 MC68302 SYSTEM ARCHITECTURE Most general-purpose microprocessor-based systems use an architecture that interfaces all ...
Page 27
CONTROLLER M68000 CORE MICROCODED COMMUNICATIONS CONTROLLER (RISC) Figure 1-3. MC68302 System Design The use of a unique arbitration scheme and synchronous transfers between the micropro- cessor and dual-port RAM gives zero wait-state operation to the M68000 microprocessor core. The dual-port ...
Page 28
General Description In the example shown in Figure 1-4, one SCC channel connects through the NMSI mode to a commercial packet data network. This connection might be used for remote status moni- toring or for maintenance functions for a system. ...
Page 29
Figure 1-4. NMSI Communications-Oriented Board Design MOTOROLA MC68302 USER’S MANUAL General Description 1-7 ...
Page 30
General Description Figure 1-5. Basic Rate IDL Voice/Data Terminal in ISDN 1-8 MC68302 USER’S MANUAL MOTOROLA ...
Page 31
SECTION 2 MC68000/MC68008 CORE The MC68302 integrates a high-speed M68000 processor with multiple communications pe- ripherals. The provision of direct memory access (DMA) control and link layer management with the serial ports allows high throughput of data for communications-intensive applica- ...
Page 32
MC68000/MC68008 Core Figure 2-1. M68000 Programming Model The supervisor's programming model includes supplementary registers, including the su- pervisor stack pointer (SSP) and the status register (SR) as shown in Figure 2-2. The SR contains the ...
Page 33
T TRACE MODE SUPERVISOR STATE INTERRUPT MASK EXTEND NEGATIVE CONDITION ZERO CODES OVERFLOW CARRY Figure 2-2. M68000 Status Register 2.2 INSTRUCTION SET SUMMARY The five data types supported by the M68000 on the MC68302 are bits, binary-coded deci- mal ...
Page 34
MC68000/MC68008 Core on bytes, words, or long words, and most instructions can use any of the 14 addressing modes. Combining instruction types, data types, and addressing modes provides over 1000 useful instructions. These instructions include signed and unsigned multiply and ...
Page 35
Table 2-2. M68000 Instruction Set Summary Mnemonic Description ABCD Add Decimal with Extend ADD Add AND Logical AND ASL Arithmetic Shift Left ASR Arithmetic Shift Right Bcc Branch Conditionally BCHG Bit Test and Change BCLR Bit Test and Clear BRA ...
Page 36
MC68000/MC68008 Core Table 2-3. M68000 Instruction Type Variations Instruction Variation Type ADD ADDA ADD ADDQ ADDI ADDX AND ANDI AND ANDI to CCR ANDI to SR CMP CMPA CMP CMPM CMPI EOR EORI EOR EORI to CCR EORI to SR ...
Page 37
Other bus masters besides the M68000 may also output function codes during their bus cy- cles. On the MC68302, this capability is provided for each potential internal bus master (i.e., the IDMA, SDMA, and DRAM refresh units). Also on the ...
Page 38
MC68000/MC68008 Core Once the processor is in the user state and executing instructions, only exception process- ing can change the privilege state. During exception processing, the current state of the S bit in the SR is saved and the S ...
Page 39
Table 2-5. M68000 Exception Vector Assignment 16– 100 26 104 27 108 28 112 29 116 30 120 31 124 128 ...
Page 40
MC68000/MC68008 Core (read/write): write = 0, read = 1 I/N (instruction not): instruction = 0, not =1 FC: Function Code Figure 2-3. M68000 Bus/Address Error Exception Stack Frame 7 15 SSP Figure 2-4. M68000 Short-Form Exception Stack ...
Page 41
INTERRUPT PROCESSING Seven interrupt levels are provided by the M68000 core. If the IMP's interrupt controller is placed in the normal mode, six levels are available to the user. If the interrupt controller is in the dedicated mode, three ...
Page 42
MC68000/MC68008 Core 2.7 MC68302 IMP CONFIGURATION CONTROL Four reserved entries in the external M68000 exception vector table (see Table 2-5) are used as addresses for internal system configuration registers. These entries are at locations $0F0, $0F4, $0F8, and $0FC. The ...
Page 43
BAR is a 16-bit value within the BAR entry and is located at $0F2. After a total system reset, the on-chip peripheral base address is undefined, and it is not possible to access the ...
Page 44
MC68000/MC68008 Core CFC—Compare Function Code 0 = The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with- out comparing the FC bits The FC bits in the BAR are compared. The address ...
Page 45
When any SCC, SCP, or SMC channel buffer descriptors or parameters are not used, their parameter RAM area can be used for additional memory. For detailed informa- tion about the use of the buffer descriptors and protocol parameters in ...
Page 46
MC68000/MC68008 Core Base + 580 • • • Base + 5BF Base + 5C0 • • • Base + 5FF Base + 600 Base + 608 Base + 610 Base + 618 Base + 620 Base + 628 Base + ...
Page 47
All undefined and reserved bits within registers and parameter RAM values written by the user in a given application should be written with zero to allow for future enhancements to the device. Address Name Width Base + 800 RES Base ...
Page 48
MC68000/MC68008 Core Base + 840 TMR1 Base + 842 TRR1 Base + 844 TCR1 Base + 846 TCN1 Base + 848 RES ! Base + 849 TER1 Base + 84A WRR Base + 84C WCN Base + 84E RES Base ...
Page 49
Base + 8A0 RES Base + 8A2 SCON3 Base + 8A4 SCM3 Base + 8A6 DSR3 ! Base + 8A8 SCCE3 Base + 8A9 RES Base + 8AA SCCM3 Base + 8AB RES Base + 8AC SCCS3 Base + 8AD ...
Page 50
MC68000/MC68008 Core 2. To clear bits 0 and 1 of SCC1, execute "MOVE.B #$03,SCCE1” clear all bits in SCCE1, execute "MOVE.B #$ff,SCCE1" where SCCE1 is equated to the actual address of SCCE1. DO NOT use read-modify-write instructions to ...
Page 51
SECTION 3 SYSTEM INTEGRATION BLOCK (SIB) The MC68302 contains an extensive SIB that simplifies the job of both the hardware and software designer. It integrates the M68000 core with the most common peripherals used in an M68000-based system. The independent ...
Page 52
System Integration Block (SIB) 3.1 DMA CONTROL The IMP includes seven on-chip DMA channels, six serial DMA (SDMA) channels for the three serial communications controllers (SCCs) and one IDMA. The SDMA channels are discussed in 4.2 SDMA Channels. The IDMA ...
Page 53
The maximum transfer rate is calculated from the fact that 16 bits are moved every 8 clocks. The calculation is as follows: 16 bits x 16M clocks/sec (2 bus cycles clocks/bus cycle) The IDMA controller block diagram is ...
Page 54
System Integration Block (SIB) (DAPR), an 8-bit function code register (FCR), a 16-bit byte count register (BCR), a 16-bit channel mode register (CMR), and an 8-bit channel status register (CSR). These registers provide the addresses, transfer count, and configuration information ...
Page 55
An interrupt will only be generated if the IDMA bit is set in the IMR. REQG—Request Generation The following decode shows the definitions for the REQG bits Internal request at limited rate (limited burst bandwidth) set by burst ...
Page 56
System Integration Block (SIB) These percentages are valid only when using internal limited re- quest generation (REQG = 00). RST—Software Reset This bit will reset the IDMA to the same state as an external reset. The IDMA clears RST when ...
Page 57
The DAPR contains 24 (A23–A0) address bits of the destination operand used by the IDMA to access memory or memory-mapped peripheral controller registers. During the IDMA write cycle, the address on the master address bus is driven from this register. ...
Page 58
System Integration Block (SIB) DNS—Done Not Synchronized This bit is set if operand packing is performed between 16-bit memory and an 8-bit periph- eral and the DONE signal is asserted as an input to the IDMA (i.e., by the peripheral) ...
Page 59
IDMA Operational Description Every IDMA operation involves the following steps: IDMA channel initialization, data trans- fer, and block termination. In the initialization phase, the M68000 core (or external proces- sor) loads the registers with control information, address pointers and ...
Page 60
System Integration Block (SIB) 3.1.4.3 Address Sequencing The manner in which the DAPR and SAPR are incremented during a transfer depends on the programming of the SAPI and DAPI bits, the source and destination sizes (DSIZE and SSIZE), and the ...
Page 61
Source Source Size Address Even 16 Odd 16 Even 16 Even 16 Odd 16 Odd * - Considered as 2 operands. 3.1.4.4 Transfer Request Generation IDMA transfers may be initiated by either internally ...
Page 62
System Integration Block (SIB) DREQ input to the IDMA is level-sensitive and is sampled at certain points to determine when a valid request is asserted by the device. The device requests service by asserting DREQ and leaving it asserted. In ...
Page 63
External Device Termination If desired, a transfer may be terminated by the device even before the BCR is decrement zero. If DONE is asserted one setup time prior to the S5 falling edge (i.e., before or with DTACK) ...
Page 64
System Integration Block (SIB) 3.1.6 DMA Bus Arbitration The IDMA controller uses the M68000 bus arbitration protocol to request bus mastership be- fore entering the DMA mode of operation. The six SDMA channels have priority over the IDMA and can ...
Page 65
Reset Upon an external chip reset, the IDMA channel immediately aborts the channel operation, returns to the idle state, and clears CSR and CMR (including the STR bit bus cycle is in progress when reset is detected, ...
Page 66
System Integration Block (SIB) • DTACK Generation When Vectors Supplied Internally 3 TIMERS 1 SCP 2 SMCs 2 DMA 4 PB8-PB11 SCC1 EVENT REGISTER (8 BITS) SCC1 MASK REGISTER (8 BITS) SCC2 EVENT REGISTER (8 BITS) SCC2 MASK REGISTER (8 ...
Page 67
The interrupt controller recognizes the interrupt acknowledge cycle and places the in- terrupt vector for that interrupt request onto the M68000 bus. 4. The M68000 reads the vector, reads the ...
Page 68
System Integration Block (SIB) Dedicated Mode In this mode, the three interrupt request pins are configured as IRQ7, IRQ6, and IRQ1 to provide dedicated request lines for three external sources at priority levels 1, 6, and 7. Each of these ...
Page 69
Table 3-3 indicates the interrupt levels available in both normal and dedicated modes. This table also shows the IPL2–IPL0 encoding that should be provided by external logic for each EXRQ interrupt level in normal mode. For the dedicated mode, this ...
Page 70
System Integration Block (SIB) requests, if any, are then assessed by priority so that another interrupt request may be presented to the core. 2. The 3-bit mask in the M68000 core status register (SR) ensures that a subsequent in- terrupt ...
Page 71
SCCE EVENT BIT SCCM MASK BIT Figure 3-3. Interrupt Request Logic Diagram for SCCs 3.2.4 Interrupt Vector Pending EXRQ interrupts and unmasked INRQ interrupts are presented to the M68000 core in order of priority. The M68000 core responds to an ...
Page 72
System Integration Block (SIB) Option 2. The external peripheral can generate the vector. In this case the external device must decode the interrupt acknowledge cycle, put out the 8-bit vector, and generate DTACK. The decoding of the interrupt acknowledge cycle ...
Page 73
Table 3-5. Encoding the Interrupt Vector Priority Level 7 (Highest (Lowest) 1. FORMULATE 8-BIT VECTOR V7– ...
Page 74
System Integration Block (SIB) 3.2.5 Interrupt Controller Programming Model The user communicates with the interrupt controller using four registers. The global interrupt mode register (GIMR) defines the interrupt controller's operational mode. The interrupt pending register (IPR) indicates which INRQ interrupt ...
Page 75
ET7—IRQ7 Edge-/Level-Triggered This bit is valid only in the dedicated mode Level-triggered. An interrupt is made pending when IRQ7 is low. The M68000 always treats level edge-sensitive interrupt. Normally, users should not select the level-triggered ...
Page 76
System Integration Block (SIB) While in disable CPU mode, during the host processor interrupt acknowledge cycle for IRQ1, if IRQ1 is not continuously assert- ed, the interrupt controller will still provide the vector number (and DTACK) according to the IV1 ...
Page 77
Interrupt Mask Register (IMR) Each bit in the 16-bit IMR corresponds to an INRQ interrupt source. The user masks an in- terrupt source by clearing the corresponding bit in the IMR. When a masked INRQ interrupt occurs, the corresponding ...
Page 78
System Integration Block (SIB) 3.2.5.4 Interrupt In-Service Register (ISR). Each bit in the 16-bit ISR corresponds to an INRQ interrupt source vectored interrupt environment, the interrupt controller sets the ISR bit when the vector number corresponding to the ...
Page 79
Immediately read the SCC1 event (SCCE1) register into a temporary location. 3. Decide which events in the SCCE1 will be handled in this handler and clear those bits in the SCCE1 as soon as possible. (Handle events in the ...
Page 80
System Integration Block (SIB) INPUT BUFFER TO PADAT BIT 0 OUTPUT LATCH 0 RXD2 TO MUX SCC2 1 EN Figure 3-5. Parallel I/O Block Diagram for PA0 When acting as a general-purpose I/O pin, the signal direction for that pin ...
Page 81
Ta- ble 3- input pin to a channel (for example CD2 or CTS2) is used as a general-purpose I/O pin, then ...
Page 82
System Integration Block (SIB) Table 3-7 shows the dedicated function of each pin. The third column shows the input to the peripheral when the pin is used as a general-purpose I/O pin. PBCNT Bit = 1 Pin Function IACK7 IACK6 ...
Page 83
Port A Control Register(PACNT I Peripheral Port A Data Direction Register(PADDR Input 1 = ...
Page 84
System Integration Block (SIB) nously with no wait states. The external master requests the M68000 bus using the BR pin and is granted bus ownership. The external master must then access the RAM synchro- nously with respect to the IMP ...
Page 85
CP µCODE ADDRESS INTERNAL PERIPHERAL ADDRESS BUS M68000 SYSTEM ADDRESS BUS 3.5 TIMERS The MC68302 includes three timer units: two identical general-purpose timers and a soft- ware watchdog timer. Each general-purpose timer consists of a timer mode register (TMR), a ...
Page 86
System Integration Block (SIB) GENERAL-PURPOSE TIMERS TIMER 2 TIMER 1 7 TER1 15 MODE REGISTER TMR1 PRESCALER DIVIDER 15 TIMER COUNTER TCN1 15 TRR1 REFERENCE REGISTER 15 TCR1 CAPTURE REGISTER WATCHDOG TIMER 15 TCN3 TIMER COUNTER 15 TRR3 REFERENCE REGISTER ...
Page 87
The watchdog timer has the following features: • A 16-Bit Counter and Reference Register • Maximum Period of 16.78 Seconds (at 16 MHz) • 0.5 ms Resolution (at 16 MHz) • Output Signal (WDOG) • Interrupt Capability 3.5.2 General Purpose ...
Page 88
System Integration Block (SIB) RST—Reset Timer This bit performs a software reset of the timer identical to that of an external reset Reset timer (software reset), includes clearing the TMR, TRR, and TCN Enable timer ICLK—Input ...
Page 89
When working in the MC68008 mode (BUSW is low), writing the high byte of TRR1 and TRR2 will disable the timer's compare logic until the low byte is written. TRR1 and TRR2 are set to all ones by reset. The ...
Page 90
System Integration Block (SIB) REF—Output Reference Event The counter has reached the TRR value. The ORI bit in the TMR is used to enable the interrupt request caused by this event. Bits 7–2—Reserved for future use. 3.5.2.6 General Purpose Timer ...
Page 91
ICLK = 01 to use the master clock, and RST = 1 to enabled the timer). Fine adjustments can be made to the timer by varying the TRR up or down. 3.5.3 Timer 3 - ...
Page 92
System Integration Block (SIB) 15 3.5.3.3 Software Watchdog Counter (WCN) WCN, a 16-bit up-counter, appears as a memory-mapped register and may be read at any time. Clearing EN in WRR causes the counter to be reset and disables the count ...
Page 93
DTACK generation occurs under the same constraints as the chip-select signal—if the chip- select signal does not activate, then neither will the DTACK signal. Chip select 0 has the special property of being enabled upon system reset to the address ...
Page 94
System Integration Block (SIB) R/W CS0 Figure 3-9. Chip-Select Block Diagram The user should not normally program more than one chip-select line to the same area. When this occurs, the address compare logic will set address decode conflict (ADC) in ...
Page 95
SCR), will not activate the chip-select lines. Thus conve- nient to use one of the chip-select lines to select external ROM/ RAM that overlaps these register addresses, since, in this way, bus contention is completely avoided during a ...
Page 96
System Integration Block (SIB) address match exists within its address space and, therefore, whether to assert the chip- select line. 111 = Not supported; reserved. Chip select will not assert if this value is chosen. 110 = Value may be ...
Page 97
EN—Enable 0 = The chip-select line is disabled The chip-select line is enabled. After system reset, only CS0 is enabled; CS3–CS1 are disabled. In disable CPU mode, CS3–CS0 are disabled at system reset. The chip select does not ...
Page 98
System Integration Block (SIB) Do not assert DTACK externally when it is programmed to be generated internally. Bits 12–2—Base Address Mask These bits are used to set the block size of a particular chip-select line. The address com- pare logic ...
Page 99
Calculate what the mask should be. For a 1 Megabyte block, the address lines A0 through A19 are used to address bytes within the block, so they need to be masked out. 2. Write $3E00 to OR2 (DTACK=1 for ...
Page 100
System Integration Block (SIB) EXTAL can also accept a CMOS-level clock input. The crystal output (XTAL) connects the internal crystal generator output to an external crystal external clock is used, XTAL should be left unconnected. The CLKO pin, ...
Page 101
Bit IPA Interrupt Priority Active HWT Hardware Watchdog Timeout WPV Write Protect Violation ADC Address Decode Conflict ERRE External RISC Request Enable VGE Vector Generation Enable WPVE Write Protect Violation Enable RMCST Read-Modify-Write Cycle Special Treatment EMWS External Master Wait ...
Page 102
System Integration Block (SIB) this happens and that other pending interrupts at the same orig- inal priority level also execute with BCLR continuously asserted, the following technique may be used. Using a parallel I/O line connected to the IRQ1 line, ...
Page 103
WPV will be set, regardless of the value of WPVE. RMCST—RMC Cycle Special Treatment 0 = The locked read-modify-write cycles of the TAS instruction will be identical to the M68000 (AS and CS will be asserted during the entire cycle). ...
Page 104
System Integration Block (SIB) After system reset, this bit defaults to zero. If BCLM is set, then the typical maximum inter- rupt latency is about 78 clocks in a zero-wait-state system. This assumes a standard instruc- tion mix, that the ...
Page 105
BG will be an input to the IDMA and SDMA from the external M68000 bus, rather than being an output from the MC68302. When BG is sampled as low by the MC68302, it waits for AS, BERR, HALT, and ...
Page 106
System Integration Block (SIB) questing the M68000 bus with BR. See 3.8.6 Hardware Watchdog for further details. 3.8.5 Bus Arbitration Logic Both internal and external bus arbitration are discussed in the following paragraphs. 3.8.5.1 Internal Bus Arbitration The IMP bus ...
Page 107
M68000 CORE INDEPENDENT DMA SERIAL DMA BGACK (IR & ER IDLE IR & CG & & & CG MOTOROLA RMC CBR CBG IPEND IDBR IDBG IBCLR SDBG ...
Page 108
System Integration Block (SIB) Table 3-10. Bus Arbitration Priority Table BCLR Ignored BCLM = 0 BR Pin SDMA SDMA IDMA IDMA BR Pin M68000 Interrupts M68000 Interrupts M68000 M68000 NOTES: 1. The SDMA on a given IMP always has a ...
Page 109
When an external master desires to gain ownership, the standard M68000 bus arbitration protocol should be used: 1. Issue BR (to the IMP on-chip bus arbiter). 2. Wait for BG (from the IMP on-chip bus arbiter). 3. When BG is ...
Page 110
System Integration Block (SIB) HWDCN–HWDCN0—Hardware Watchdog Count 2–0 000 = BERR is asserted after 128 clock cycles (8 s, 16-MHz clock) 001 = BERR is asserted after 256 clock cycles (16 s, 16-MHz clock) 010 = BERR is asserted after ...
Page 111
At the end of the STOP instruction, a major change to the IMP occurs. The M68000 core immediately goes into a standby state in which it executes no instructions. In this state, the clock internally sent to the M68000 core ...
Page 112
System Integration Block (SIB) 3.8.7.2.2 Lowest Power Mode In this mode, the processor frequency can be further reduced beyond the minimum system frequency limit (e.g., lower than the limit of 8 MHz). In this mode, the LPREC bit must be ...
Page 113
A SCC Performance). Also, the minimum 1:2.5 serial to CLKO clock ratio must be maintained at all times. The following list gives a step-by-step example of how to achieve the lowest possible power using an external clock. For this ...
Page 114
System Integration Block (SIB) LPP16—Low-power Clock Prescale Divide The low-power clock divider input clock is the main clock The low-power clock divider input clock is the main clock divided by 16. Thus, a divide ...
Page 115
An external pullup should be used if TCLK1 is not driven externally. TSTCLK1 may be toggled at any time, but the SCC1 transmitter should be disabled and re-enabled if any dynamic change is made on TSTCLK1 during the ...
Page 116
System Integration Block (SIB) FRZ1—Freeze Timer 1 Enable 0 = Freeze timer 1 logic is disabled Freeze timer 1 logic is enabled. After system reset, this bit defaults to zero. FRZ2—Freeze Timer 2 Enable 0 = Freeze timer ...
Page 117
DRAM bank. The PAL generates the RAS and CAS lines for the DRAM chips and con- trols the address multiplexing in the external address buffers. One of the MC68000 chip-se- lect lines can be used as the DRAM ...
Page 118
System Integration Block (SIB) 3.10.4 Initialization The user should first initialize the refresh routine parameters in the SCC2 parameter RAM. These parameters are the DRAM low starting address, the DRAM high starting address, the DRAM address increment step (number of ...
Page 119
DRAM_Low—Dynamic RAM Low Address This 16-bit parameter contains the lower 16 bits of the dynamic RAM starting address. This parameter should be initialized by the user before activating the refresh routine. INCREMENT—Increment Step This 16-bit parameter contains the number of ...
Page 120
System Integration Block (SIB) 3-70 MC68302 USER’S MANUAL MOTOROLA ...
Page 121
SECTION 4 COMMUNICATIONS PROCESSOR (CP) The CP includes the following modules: • Main Controller (RISC Processor) • Six Serial Direct Memory Access (SDMA) Channels • A Command Set Register • Serial Channels Physical Interface Including: —Motorola Interchip Digital Link (IDL) ...
Page 122
Communications Processor (CP) buffer descriptors of the serial channels. Also, a number of protocol-specific parameters are exchanged through several parameter RAM areas in the internal dual-port RAM. The RISC controller uses the peripheral bus to communicate with all its peripherals. ...
Page 123
DRAM Refresh Controller 4. Commands Issued to the Command Register 5. SCC1 Receive Channel 6. SCC1 Transmit Channel 7. SCC2 Receive Channel 8. SCC2 Transmit Channel 9. SCC3 Receive Channel 10. SCC3 Transmit Channel 11. SMC1 Receive Channel 12. ...
Page 124
Communications Processor (CP) CONTROLLER M68000 CORE MICROCODED COMMUNICATIONS CONTROLLER (RISC) Figure 4-2. Three Serial Data Flow Paths The SDMA channels implement bus-cycle-stealing data transfers controlled by microcode in the CP main controller. Having no user-accessible registers associated with them, the ...
Page 125
The SDMA will assert the external BCLR pin when it requests the bus. BCLR can be used to clear an external bus master from the external bus, if desired. For instance, BCLR can be connected through logic to the external ...
Page 126
Communications Processor (CP) OPCODE—Command Opcode These bits are set by the M68000 core to define the specific SCC command. The precise meaning of each command below depends on the protocol chosen STOP TRANSMIT Command 01 = RESTART TRANSMIT ...
Page 127
FLG—Command Semaphore Flag The bit is set by the M68000 core and cleared by the CP The CP is ready to receive a new command The CR contains a command that the CP is currently processing. ...
Page 128
Communications Processor (CP) RTS, CTS, and CD are multiplexed with the SCP. See 4.6 Serial Communication Port (SCP) for more details on the SCP. MC68302 BRG1 BRG2 BRG3 NMSI — Nonmultiplexed serial interface (also called the modem I/F). Figure 4-3. ...
Page 129
SCC1 BRG1 BRG SCC2 TCLK2 BRG OR BRG2 SCC3 TCLK3 BRG OR BRG3 Figure 4-4. Multiplexed Mode on SCC1 Opens Additional There are five serial channel physical interface combinations for the three SCCs (see Table 4-1). Table 4-1. The Five ...
Page 130
Communications Processor (CP) When using the IDL or GCI buses, additional control functions in the frame structure are re- quired. These functions are supported in the MC68302 through two SMC channels: SMC1 and SMC2. (For other matters relating to the ...
Page 131
IDL Interface The IDL interface is a full-duplex ISDN interface used to interconnect a physical layer device (such as the Motorola ISDN S/T transceiver MC145474) to the integrated multiprotocol pro- cessor (IMP). Data on five channels (B1, B2, D, ...
Page 132
Communications Processor (CP) terminal data stream over the B channel. That SCC would be configured for HDLC mode if V.120 rate adaption is required, or for V.110 mode if V.110 rate adaption is required. The second B channel could be ...
Page 133
L1CLK IDL clock; input to the IMP. IDL transmit data; output from the IMP. Valid only for the bits that L1TXD are supported by the IDL; three-stated otherwise. IDL receive data; input to the IMP. Valid for the 20 bits ...
Page 134
Communications Processor (CP) The IDL interface supports the CCITT I.460 recommendation for data rate adaptation. The IDL interface can access each bit of the B channel as an 8-kbps channel. A serial interface mask register (SIMASK) for the B channels ...
Page 135
L1SY1 L1CLK (L1CLK is 2x data rate) L1TXD B1 8 L1RXD B1 SCC1–SCC3 The GCI signals are as follows: L1CLK GCI clock; input to the IMP. L1TXD GCI transmit data; open drain output. L1RXD GCI receive data; input to the ...
Page 136
Communications Processor (CP) The monitor channel is used to transfer data between layer-1 devices and the control unit (i.e., the M68000 core). The command/indication channel is used to control activation/deac- tivation procedures or for the switching of test loops by ...
Page 137
Table 4-2. PCM Highway Mode Pin Functions Signal L1RXD L1TXD L1CLK L1SY0 L1SY1 RTS1, RTS2, RTS3 L1CLK is always an input to the MC68302 in PCM highway mode and is used as both a re- ceive and transmit clock. Thus, ...
Page 138
Communications Processor (CP) have to be contiguous in the PCM highway, but rather can be separated by other time slots. Also, PCM channel time slots need not be an even multiple of eight bits in envelope mode. Although not shown ...
Page 139
L1TXD 8 BITS 8 BITS 8 BITS L1RXD L1CLK L1SY0 L1SY1 PCM CHANNEL 1 CONTAINS 8 BITS AND CAN BE ROUTED TO ANY SCC. NOTE: Whenever the syncs are active, data from that SCC is transmitted ...
Page 140
Communications Processor (CP) NMSI mode. The SIMODE register is a memory-mapped read-write register cleared by re- set SETZ SYNC/SCIT SDIAG1 7 6 B1RB B1RA DRB SETZ—Set L1TXD to zero (valid only for the GCI interface ...
Page 141
SDC2—Serial Data Strobe Control SDS2 signal is asserted during the B2 channel 1 = SDS1 signal is asserted during the B2 channel SDC1—Serial Data Strobe Control SDS1 signal is asserted during the B1 channel ...
Page 142
Communications Processor (CP) three SCC3 functions (CTS3, RTS3, and CD3) can be routed to replace the three SCP pins or else not used. In NMSI mode, the MSC2 and MSC3 bits are ignored. The choice of general-pur- pose I/O port ...
Page 143
PCM highway. Each protocol-type implementation uses identical buffer structures to simplify programming. The following protocols are supported: HDLC/SDLC, BISYNC, synchronous and asynchro- nous DDCMP, UART, several transparent modes, and V.110 rate adaption support. Each protocol can ...
Page 144
Communications Processor (CP) SCC STATUS SCC DATA SYNC REGISTER REGISTER RECEIVER CONTROL UNIT DELIMITER RXD 4.5.1 SCC Features Each SCC channel has the following features: • HDLC/SDLC, BISYNC, DDCMP, UART, Transparent, or V.110 Protocols • Programmable Baud Rate Generator Driven ...
Page 145
Each SCON is a 16-bit, memory-mapped, read-write register. The SCONs are set to $0004 by reset, resulting in the baud rate generator output clock rate being set to the main clock rate divided by 3. The baud rate generator output ...
Page 146
Communications Processor (CP) CD10–CD0—Clock Divider The clock divider bits and the prescaler determine the baud rate generator output clock rate. CD10–CD0 are used to preset an 11-bit counter that is decremented at the prescaler output rate. The counter is not ...
Page 147
UART clock on the TCLK or RCLK pins can be as high as 6.67 MHz, giving a maximum baud rate of 417 kbaud. The baud rate using the baud rate generator is (System Clock or TIN1 ...
Page 148
Communications Processor (CP) If RTS is programmed to be asserted by the SCC, it will be asserted once buffered data is loaded into the transmit FIFO and a falling TCLK edge occurs. The following table shows the transmit data delays. ...
Page 149
I/O lines in the PACNT register. To cause the TXD and RTS pins to simply remain high in NMSI1, NMSI2, and NMSI3 modes, use this loopback mode in con- junction with setting the SDIAG1–SDIAG0 bits in the SIMODE register ...
Page 150
Communications Processor (CP) for an internal clock, TCS and RCS may both be zero, or, for an external clock, they may both be one. The other two combinations are not allowed in this mode. If external loopback is desired (i.e., ...
Page 151
ENT bit, 3) the STOP TRANSMIT command, 4) the RESTART TRANSMIT command, and 5) the FRZ bit in the SCM (UART mode only). ENR—Enable Receiver When ENR ...
Page 152
Communications Processor (CP) 4.5.5 Buffer Descriptors Table Data associated with each SCC channel is stored in buffers. Each buffer is referenced by a buffer descriptor (BD). BDs are located in each channel's BD table (located in dual-port RAM). There are ...
Page 153
OFFSET + 0 OFFSET + 2 OFFSET + 4 HIGH-ORDER DATA BUFFER POINTER (only lower 8 bits used, upper 8 bits must be 0) OFFSET + 6 Figure 4-16. SCC Buffer Descriptor Format For frame-oriented protocols (HDLC, BISYNC, DDCMP, ...
Page 154
Communications Processor (CP) table, after processing of this BD is complete. After using a BD, the CP sets the “ready” bit to not-ready; thus, the CP will never use a BD twice until the BD has been confirmed by the ...
Page 155
Table 4-6. SCC Parameter RAM Memory Map Address Name SCC Base + 80 # RFCR SCC Base + 81 # TFCR SCC Base + 82 # MRBLR SCC Base + 84 ## SCC Base + 86 ## SCC Base + ...
Page 156
Communications Processor (CP) 4.5.6.2 Maximum Receive Buffer Length Register (MRBLR) Each SCC has one MRBLR that is used to define the receive buffer length for that SCC. The MRBLR defines the maximum number of bytes that the IMP will write ...
Page 157
Other General Parameters Additional parameters are listed in Table 4-2. These parameters do not need to be accessed by the user in normal operation, and are listed only because they may provide helpful infor- mation for experienced users and ...
Page 158
Communications Processor (CP) (i.e., NMSI, PCM, GCI, IDL modes). If IDL or GCI is chosen in SIMODE, write SIMASK in the serial channels physical interface (see 4.4.5 Serial Interface Registers). 3. Write SCON (see 4.5.2 SCC Configuration Register (SCON)). 4. ...
Page 159
Bit manipulation instructions such as BSET should not be used to clear bits in the event register because any bits that were set will be written back as ones (thus clearing all pending interrupts) as well as the desired bit. ...
Page 160
Communications Processor (CP) gardless of what happens externally. This signifies that the cor- responding SCCS bit is now valid. 7 Bits 7–3—Reserved for future use. ID—Idle Status on the Receiver Line This bit is meaningful only if the SCC is ...
Page 161
Tx Channel 5—SCC3 Rx Channel Next, the pointer that caused the bus error can be determined by reading the inter- nal data pointer from the parameter's memory map of the particular SCC. Following this bus error, ...
Page 162
Communications Processor (CP) Totally Transparent (Promiscuous) Mode The MC68302 can both receive and transmit the entire serial bit stream transparently. See 4.5.16 Transparent Controller for details. 4.5.10 Disabling the SCCs If an SCC transmitter or receiver is not needed for ...
Page 163
The SCC should be disabled and re-enabled if any change is made to the SCC's parallel I/O or serial channels physical interface configuration. The SCC does not need to be dis- abled if only a change to a parameter RAM ...
Page 164
Communications Processor (CP) Since the transmitter and receiver work asynchronously, there is no need to connect trans- mit and receive clocks. Instead, the receiver over-samples the incoming data stream by a factor of 16 and uses some of these samples ...
Page 165
Other modem lines such as data set ready (DSR) and data terminal ready (DTR) can be supported through the parallel I/O pins. The UART consists of separate transmit and receive sections whose operations are asyn- chronous with the M68000 ...
Page 166
Communications Processor (CP) The UART may receive fractional stop bits. The next character's start bit may begin anytime after the 11th internal clock of the previous character's first stop bit (the UART uses a 16X clock). The UART transmit shift ...
Page 167
MAX_IDL The UART controller watches the receive line, regardless of whether or not actual data is being received. If the line is idle, the UART controller counts how many idle characters have been received. An idle character is defined as ...
Page 168
Communications Processor (CP) RCCR, CHARACTER The UART controller can automatically recognize special characters and generate inter- rupts. It also allows a convenient method for inserting flow control characters into the transmit stream. See 4.5.11.7 UART Control Characters and Flow Control ...
Page 169
UART Command Set These commands are issued to the command register described in 4.3 Command Set. STOP TRANSMIT Command After a hardware or software reset and the enabling of the channel by writing the SCC mode register, the channel ...
Page 170
Communications Processor (CP) 4.5.11.6 UART Address Recognition In multidrop systems, more than two stations may be present on a network, with each having a specific address. Figure 4-18 shows two examples of such a configuration. Frames com- prised of many ...
Page 171
UART Control Characters and Flow Control The UART has the capability to recognize special control characters. These characters may be used when the UART functions in a message-oriented environment eight control characters may be defined by the ...
Page 172
Communications Processor (CP) E—End of Table 0 = This entry is valid. The lower eight bits will be checked against the incoming char- acter The entry is not valid. No valid entries lie beyond this entry. In tables ...
Page 173
CT—Clear-to-Send Lost This status bit indicates that the CTS signal was negated during transmission of this char- acter. If this occurs, the CTS bit in the UART event register will also be set. If the CTS signal was negated during ...
Page 174
Communications Processor (CP) character consecutive ones (if UM1–UM0 = 00 the address bit of the next message (if UM0 = 1). When the receiver is in sleep mode and a break sequence is received, ...
Page 175
IDLE Sequence. Receive IDLE (preamble) is detected by the UART controller when a character with consecutive ones (depending on the UM1–UM0, SL, PEN, and CL bits in the UART mode register) is received. When ...
Page 176
Communications Processor (CP) 4.5.11.13 UART Mode Register. Each SCC mode register is a 16-bit, memory- mapped, read-write register that controls the SCC operation. The term UART mode register refers to the protocol-specific bits (15–6) of the SCC mode register when ...
Page 177
No address recognition is performed The DDCMP protocol is implemented over the asynchronous channel Multidrop mode is enabled as in the 01 case, and the ...
Page 178
Communications Processor (CP) 5. Reception of an address character when working in multidrop mode OFFSET + OFFSET + 2 OFFSET + 4 OFFSET +6 Figure 4-20. UART Receive Buffer Descriptor The ...
Page 179
RECEIVE STATUS 0 LENGTH 0008 32-BIT BUFFER POINTER POINTER (24-BITS USED) RECEIVE STATUS LENGTH 0002 32-BIT BUFFER POINTER POINTER (24-BITS USED) RECEIVE STATUS 0 0 ...
Page 180
Communications Processor (CP) I—Interrupt interrupt is generated after this buffer has been filled The RX bit in the UART event register will be set when this buffer has been com- pletely filled by the CP, ...
Page 181
CD—Carrier Detect Lost The carrier detect signal was negated during message reception. Data Length Data length contains the number of octets written by the CP into this BD's data buffer written by the CP once as the BD ...
Page 182
Communications Processor (CP) X—External Buffer 0 = The buffer associated with this internal dual-port RAM The buffer associated with this external memory. W—Wrap (Final BD in Table This is not ...
Page 183
CT—CTS Lost 0 = The CTS signal remained active during transmission The CTS signal was negated during transmission. Data Length The data length is the number of octets that the CP should transmit from this BD's data buffer. ...
Page 184
Communications Processor (CP) CHARACTERS RECEIVED BY UART TIME RXD LINE IDLE CD UART SCCE CD IDL EVENTS NOTES: 1. The first RX event assumes receive buffers are six bytes each. 2. The second IDL event occurs after ...
Page 185
BRK—Break Character Received A break character was received. CCR—Control Character Received A control character was received (with reject (R) character = 1) and stored in the receive control character register (RCCR). BSY—Busy Condition A character was received and discarded due ...
Page 186
Communications Processor (CP) Three characters should first be entered into the UART control character table: 1. End of Line—The empty (E) bit is cleared; the reject (R) bit is cleared. When an end- of-line character is received, the current buffer ...
Page 187
The 8- or 16-bit control field provides a flow control number and defines the frame type (con- trol or data). The exact use and structure of this field depends upon the protocol using the frame. Data is transmitted in the ...
Page 188
Communications Processor (CP) • Detection of Non-Octet Aligned Frames • Detection of Frames That Are Too Long • Programmable Flags (0–15) between Successive Frames • Automatic Retransmission in Case of Collision 4.5.12.1 HDLC Channel Frame Transmission Processing The HDLC transmitter ...
Page 189
HDLC controller will fetch the next BD in the table and empty, will continue to transfer the rest of the frame to this BD's associated data buffer. During this ...
Page 190
Communications Processor (CP) The HDLC controller uses the same data structure as the UART, BISYNC, and DDCMP con- trollers. This data structure supports multibuffer operation and address comparisons. The receive errors (overrun, nonoctet aligned frame, CD lost, aborted frame, and ...
Page 191
ENTER HUNT MODE Command After a hardware or software reset and the enabling of the channel by its SCC mode reg- ister, the channel is in the receive enable mode and will use the first BD in the table. The ...
Page 192
Communications Processor (CP) and the frame length in the last BD. MFLR is defined as all the in-frame bytes between the opening flag and the closing flag (address, control, data, and CRC). MAX_CNT is a tempo- rary downcounter used to ...
Page 193
BD, and generates the RXF interrupt (if enabled). This error has the highest ...
Page 194
Communications Processor (CP) the SCC mode register when that SCC is configured for HDLC. The read-write HDLC mode register is cleared by reset NOF3 NOF2 NOF1 NOF0 C32 NOF3–NOF0—Minimum Number of Flags between Frames or ...
Page 195
ENC—Data Encoding Format 0 = Non-return to zero (NRZ). A one is a high level; a zero is a low level Non-return to zero inverted (NRZI). A one is represented by no change in the level; a zero ...
Page 196
Communications Processor (CP) RECEIVE STATUS 0008 LENGTH 32-BIT BUFFER POINTER POINTER (24-BITS USED) RECEIVE STATUS LENGTH 000B 32-BIT BUFFER POINTER POINTER (24-BITS USED) RECEIVE ...
Page 197
W—Wrap (Final BD in Table This is not the last BD in the Rx BD table This is the last BD in the Rx BD table. After this buffer has been used, the HDLC controller will ...
Page 198
Communications Processor (CP) CR—Rx CRC Error This frame contains a CRC error. OV—Overrun A receiver overrun occurred during frame reception. CD—Carrier Detect Lost The carrier detect signal was negated during frame reception. This bit is valid only when working in ...
Page 199
The first word of the Tx BD contains status and control bits. Bits 15–10 are prepared by the user before transmission; bits 1–0 are set by the HDLC controller after the buffer has been transmitted. Bit 15 is set by ...
Page 200
Communications Processor (CP) UN—Underrun The HDLC controller encountered a transmitter underrun condition while transmitting the as- sociated data buffer. CT—CTS Lost CTS in NMSI mode or L1GR (layer-1 grant) in IDL/GCI mode was lost during frame trans- mission. If data ...