MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 142

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
4.4.5.2 Serial Interface Mask Register (SIMASK)
The SIMASK register, a memory-mapped read-write register, is set to all ones by reset. SI-
MASK is used in IDL and GCI to determine which bits are active in the B1 and B2 channels.
Any combination of bits may be chosen. A bit set to zero is not used by the IMP. A bit set to
one signifies that the corresponding B channel bit is used for transmission and reception on
the B channel. Note that the serial data strobes, SD1 and SD2, are asserted for the entire
8-bit time slot independent of the setting of the bits in the SIMASK register.
4.5 SERIAL COMMUNICATION CONTROLLERS (SCCS)
The IMP contains three independent SCCs, each of which can implement different proto-
cols. This configuration provides the user with options for controlling up to three independent
full-duplex lines implementing bridges or gateway functions or multiplexing up to three SCCs
onto the same physical layer interface to implement a 2B + D ISDN basic rate channel or
4-22
15
01 = PCM Mode
10 = IDL Mode
11 = GCI Interface
three SCC3 functions (CTS3, RTS3, and CD3) can be routed to replace the three
SCP pins or else not used.
In NMSI mode, the MSC2 and MSC3 bits are ignored. The choice of general-pur-
pose I/O port pins versus SCC2 and SCC3 functions is made in the port A control
register. See 3.3 Parallel I/O Ports for an example and more information. The
choice of SCP pins versus three SCC3 functions is made in the SPMODE register
in the SCP. See 4.6 Serial Communication Port (SCP) for more details.
When working in PCM mode, each of the three multiplexed channels CH-1, CH-
2, and CH-3 can be routed independently to each of the three SCCs. This con-
nection is determined by the DRB, DRA, B1RB, B1RA, B2RB, and B2RA bits.
SCC2 and SCC3 can be connected directly to their respective NMSI pins (if they
are not needed for the PCM channels) as determined by the MSC3–MSC2 bits.
In the NMSI case, the choice still exists for port/SCP functions versus SCC func-
tions as described in case 00. The MSC3–MSC2 bits override the PCM routing
for a specific SCC.
When working in IDL/GCI mode, each ISDN channel (D, B1, and B2) can be rout-
ed independently to each of the three SCCs. This connection is determined by the
DRB, DRA, B1RB, B1RA, B2RB, and B2RA bits. SCC2 and SCC3 can be con-
nected directly to their respective NMSI pins (if they are not needed for ISDN
channels) determined by the MSC3–MSC2 bits. In the NMSI case, the choice still
exists for port/SCP functions versus SCC functions as described in case 00. Note
that the MSC3–MSC2 bits override the ISDN connection for a specific SCC.
Refer to the IDL mode description.
Bit 0 of this register is the first bit transmitted or received on the
IDL/GCI B1 channel.
B2
MC68302 USER’S MANUAL
NOTE
8
7
B1
MOTOROLA
0