MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 61

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.1.4.4 Transfer Request Generation
IDMA transfers may be initiated by either internally or externally generated requests. Inter-
nally generated requests can be initiated by setting STR in the CMR. Externally generated
transfers are those requested by an external device using DREQ in conjunction with the ac-
tivation of STR.
Internal Maximum Rate
Internal Limited Rate
External Burst Mode
MOTOROLA
The first method of internal request generation is a nonstop transfer until the transfer
count is exhausted. If this method is chosen, the IDMA will arbitrate for the bus and begin
transferring data after STR is set and the IDMA becomes the bus master. If no exception
occurs, all operands in the data block will be transferred in sequential bus cycles with the
IDMA using 100 percent of the available bus bandwidth (unless an external bus master
requests the bus or the M68000 core has an unmasked pending interrupt request and
BCLM = 1). See 3.1.6 DMA Bus Arbitration for more details.
To guarantee that the IDMA will not use all the available system bus bandwidth during a
transfer, internal requests can be limited to the amount of bus bandwidth allocated to the
IDMA. Programming the REQG bits to “internal limited rate” and the BT bits to limit the
percentage of bandwidth achieves this result. As soon as STR is set, the IDMA module
arbitrates for the bus and begins to transfer data when it becomes bus master. If no ex-
ception occurs, transfers will continue uninterrupted, but the IDMA will not exceed the per-
centage of bus bandwidth programmed into the control register (12.5%, 25%, 50%, or
75%). This percentage is calculated over each ensuing 1024 internal clock cycle period.
For example, if 12.5% is chosen, the IDMA will attempt to use the bus for the first 128
clocks of each 1024 clock cycle period. However, because of other bus masters, the IDMA
may not be able to take its 128 clock allotment in a single burst.
For external devices requiring very high data transfer rates, the external burst mode al-
lows the IDMA to use all the bus bandwidth to service the device. In the burst mode, the
* - Considered as 2 operands.
Source
Size
16
16
16
16
16
16
8
8
8
Address
Source
Even
Even
Even
Odd
Odd
Odd
X
X
X
Table 3-2. IDMA Bus Cycles
MC68302 USER’S MANUAL
Destination
Size
16
16
16
16
16
16
8
8
8
Destination
Address
Even
Even
Even
Odd
Odd
Odd
X
X
X
8-bit Bus
RWRW*
RWRW*
RWRW*
RWRW*
RWRW*
RWRW*
RWRW*
RWRW*
Cycles
System Integration Block (SIB)
RW
16-bit Bus
Cycles
RRWW
RRWW
RRWW
RWW
RWW
RRW
RRW
RW
RW
3-11