MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 337

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Since operation at very high data rates is characteristic of HDLC-framed channels rather
than BISYNC-, DDCMP-, or async-framed channels, the user can also use the MC68302 in
conjunction with either the Motorola MC68605 1984 CCITT X.25 LAPB controller, the
MC68606 CCITT Q.921 multilink LAPD controller, or the MC145488 dual data link control-
ler. These devices fully support operation at T1/CEPT rates (and above) and can operate
with their serial clocks "gated" onto subchannels of such an interface. These devices are full
M68000 bus masters. The MC68605 and MC68606 perform the full data-link layer protocol
as well as support various transparent modes within HDLC-framed operation. The
MC145488 provides HDLC-framed and totally transparent operation on two full-duplex
channels.
MOTOROLA
7. This data applies to MC68302 masks 2B14M, 3B14M, or later.
8. The following explanation concerns a fast HDLC channel and two slower channels: When the fast HDLC is 1:9, two
9. Performance results above showed no receive overruns or transmit underruns in several minutes of continuous
10. All results assume the DRAM refresh controller is not operating; otherwise, performance is slightly reduced.
11. Unless specifically stated, all table results assume continuous full-duplex operation. Results for half-duplex were not
channel was always SCC1.
HDLCs can run at 1:224. Thus, with a 16.67-MHz dock, SCC1 can run at 1.85 Mbps; SCC2 and SCC3 can run at 74
kbps. Two HDLCs can also run without equal values: one at 1:128 and one at 1:238. When the fast HDLC is 1:10, two
HDLCs can run at 1:128. When the fast HDLC is 1:9, two UARTs can run at 1:396 (*16). When the fast HDLC is 1:10,
two UARTs can run at 1:10 (*16).
transmission/reception. Reduction of the above ratios by a single value (e.g., 1:35 reduced to 1:34) did show an
overrun or underrun within several minutes.
measured, but will be roughly 2x better.
MC68302 USER’S MANUAL
SCC Performance
A-3