MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 197

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

W—Wrap (Final BD in Table)
I—Interrupt
The following status bits are written by the HDLC controller after the received data has been
placed into the associated data buffer.
L—Last in Frame
F—First in Frame
Bits 9–6—Reserved for future use.
LG—Rx Frame Length Violation.
NO—Rx Nonoctet Aligned Frame
AB—Rx Abort Sequence
MOTOROLA
This bit is set by the HDLC controller when this buffer is the last in a frame. This implies
the reception of a closing flag or reception of an error, in which case one or more of the
CD, OV, AB, and LG bits are set. The HDLC controller will write the number of frame oc-
tets to the data length field.
This bit is set by the HDLC controller when this buffer is the first in a frame.
A frame length greater than the maximum defined for this channel was recognized (only
the maximum-allowed number of bytes (MFLR) is written to the data buffer). This event
will not be reported until the Rx BD is closed and the RXF bit is set, after receipt of the
closing flag. The actual number of bytes received between flags is written to the data
length field of this BD.
A frame that contained a number of bits not exactly divisible by eight was received.
A minimum of seven consecutive ones was received during frame reception.
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the HDLC
0 = The RXB bit is not set after this buffer has been used, but RXF operation remains
1 = The RXB or RXF bit in the HDLC event register will be set when this buffer has
0 = This buffer is not the last in a frame.
1 = This buffer is the last in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
controller will receive incoming data into the first BD in the table.
unaffected.
been used by the HDLC controller, which can cause an interrupt.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant operation may occur.
MC68302 USER’S MANUAL
NOTE
Communications Processor (CP)
4-77