MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 380
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 380 of 481
- Download datasheet (2Mb)
MC68302 Applications
D.5.8 Final Notes
Only three signals, DREQ, DACK, and DONE, are used to control the handshake between
the peripheral and the IDMA. DONE is not needed unless the number of bytes to transmit is
not known. The DACK signal can select the peripheral device when data is being transferred
to or from it, and wait-state logic can generate DTACK to indicate when valid data is on the
bus. Software controls data transfer by setting bits in the CMR as shown in Table D-2 and
loading the SAPR and DAPR. It then waits for completion of the transfer by either monitoring
the bits in the CSR (see Table D-3) or by using interrupt processing.
D.6 MC68302 MULTIPROTOCOL CONTROLLER TIED TO IDL BUS FORMS
The following paragraphs discuss how the MC68302 can be tied to the interchip digital link
(IDL) bus, which enables connectivity to a family of ISDN chips. The IDL bus connects the
MC68302 integrated controller with the MC145475 S/T interface and the MC145554 CO-
DEC to form a basic rate ISDN voice/data terminal (see Figure D-11).
The MC68302 is the first device to combine the benefits of the M68000 microprocessor with
a flexible communications architecture. This CMOS device incorporates an MC68000 or
MC68008 core processor, a communications RISC processor with associated peripherals,
and a system integration block.
D-30
EPROM
AND ISDN VOICE/DATA TERMINAL
RAM
NON-ISDN
TERMINAL
Figure D-11. ISDN Voice/Data Terminal
SCC2
MC68302
MC68302 USER’S MANUAL
ISDN VOICE/DATA TERMINAL
IMP
SCC1
SCC3
SCP
STROBE
HANDSET
SCP BUS
IDL BUS
MC145554
CODEC
MC145475
INTERFACE
S/T
MOTOROLA
S/T
LOOP
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