MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 256
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 256 of 481
- Download datasheet (2Mb)
Communications Processor (CP)
4.6.1 SCP Programming Model
The SCP mode register consists of the upper eight bits of SPMODE. The SCP mode regis-
ter, an internal read-write register that controls both the SCP operation mode and clock
source, is cleared by reset.
STR—Start Transmit
LOOP—Loop Mode
CI—Clock Invert
PM3–PM0—Prescale Modulus Select
The prescale modulus select bits specify the divide ratio of the prescale divider in the SCP
clock generator. The divider value is 4*(“PM3–PM0” + 1) giving a clock divide ratio of 4 to
64 in multiples of 4. With a 16.384-MHz system clock, the maximum SCP clock is 4.096
MHz.
EN—Enable SCP
4-136
When set, this bit causes the SCP controller to transmit eight bits from the SCP transmit/
receive buffer descriptor (BD) and to receive eight bits of data in this same BD. This bit is
cleared automatically after one system clock cycle.
When set, the loop mode bit selects local loopback operation. The ones complement of
the transmitter output is internally connected to the receiver input; the receiver and trans-
mitter operate normally except that SPRXD is ignored. When cleared, this bit selects nor-
mal operation.
When set, the CI bit inverts the SCP clock polarity. When CI is zero, transmitted data bits
shift on rising clock edges, and received bits are sampled on falling edges. When the SCP
is idle, the clock is low. While CI is one, transmitted data bits are shifted on falling edges,
and received bits are sampled on rising edges. In this case, when the SCP is idle, the
clock is high.
When set, this bit enables the SCP operation and connects the external pins SPRXD/
CTS3, SPTXD/RTS3, and SPCLK/CD3 internally to the SCP (see Figure 4-45). When
cleared, the SCP is put into a reset state consuming minimal power, and the three pins
are connected back to SCC3.
When the DIAG1–DIAG0 bits of SCC3 are programmed to nor-
mal operation control of the CTS and CD lines and the ENT or
ENR bits of SCC3 are set, the user may not modify the EN bit.
STR
15
LOOP
14
MC68302 USER’S MANUAL
13
CI
PM3
12
NOTE
PM2
11
PM1
10
PM0
9
EN
8
MOTOROLA
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