MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 118

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
3.10.4 Initialization
The user should first initialize the refresh routine parameters in the SCC2 parameter RAM.
These parameters are the DRAM low starting address, the DRAM high starting address, the
DRAM address increment step (number of bytes in a row), the count (number of rows), and
a temporary count. Then, mask the PB8 bit in the IMR (unless an interrupt is desired on each
refresh request). Next, the timer or baud rate generator should be programmed to provide
the desired refresh clock to the PB8 pin. Next, the ERRE bit in the SCR should be set. Then,
upon every high-to-low transition of PB8, the refresh routine executes one refresh (read) cy-
cle.
ERRE—External RISC Request Enable
3.10.5 DRAM Refresh Memory Map
The DRAM refresh memory map replaces the SCC2 TxBD6 and TxBD7 structures in the
parameter RAM. The wrap bit must therefore be set in SCC2 TxBD5 so that only six TxBDs
are used for SCC2. These parameters should be written before the DRAM refresh controller
receives its first request, but may be read at any time. They are undefined at reset.
#
DRAM_High—Dynamic RAM High Address and Function Codes
This 16-bit parameter contains the dynamic RAM address space function code output during
the refresh cycle and the high eight bits of the dynamic RAM starting address. This param-
eter should be initialized by the user before activating the refresh routine.
3-68
Base + 570 #
Base + 572 #
Base + 574 #
Base + 576 #
Base + 578
Base + 57A
Base + 57C #
Base + 57E
Initialized by the user (M68000 core).
15
0
0 = Normal operation.
1 = When this bit is set, a high-to-low transition on PB8 causes the CP to execute the
Address
14
DRAM refresh routine.
The FC bits should not be programmed to the value “111.”
FC
DRAM-High
DRAM-Low
INCREMENT
COUNT
T-ptr-H
T-ptr-L
T-count
RESERVED
12
Table 3-11. DRAM Refresh Memory Map Table
Name
11
0 0 0
MC68302 USER’S MANUAL
Word
Word
Word
Word
Word
Word
Word
Word
Width
NOTE
8
Dynamic RAM High Address and FC
Dynamic RAM Low Address
Increment Step (number of bytes/row)
RAM Refresh Cycle Count (number of rows)
Temporary Refresh High Address and FC
Temporary Refresh Low Address
Temporary Refresh Cycles Count
Reserved
7
HIGH START ADDRESS
Description
MOTOROLA
0