MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 106
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 106 of 481
- Download datasheet (2Mb)
System Integration Block (SIB)
3.8.5 Bus Arbitration Logic
Both internal and external bus arbitration are discussed in the following paragraphs.
3.8.5.1 Internal Bus Arbitration
The IMP bus arbiter supports three bus request sources in the following standard priority:
When one of these sources desires the bus, the M68000 core will be forced off through an
internal bus request signal (CBR) from the bus arbiter to the M68000 core (see Figure 3-12).
When the arbiter detects the assertion of the M68000 core bus grant (CBG) signal, it asserts
the requester's bus grant signal according to its priority. Thus, as seen externally, the SDMA
and IDMA channels do not affect BR and BG, but only BGACK (unless disable CPU mode
is used).
The MC68302 provides several options for changing the preceding bus master priority list.
The options are configured by setting the BCLM bit in the SCR and deciding whether or not
the BCLR pin is used externally to cause external bus masters to relinquish the bus (see
Table 3-10).
3-56
1. External bus master (BR pin)
2. SDMA for the SCCs (six channels)
3. IDMA (one channel)
questing the M68000 bus with BR. See 3.8.6 Hardware
Watchdog for further details.
MC68302 USER’S MANUAL
MOTOROLA
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