MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 74
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
System Integration Block (SIB)
3.2.5 Interrupt Controller Programming Model
The user communicates with the interrupt controller using four registers. The global interrupt
mode register (GIMR) defines the interrupt controller's operational mode. The interrupt
pending register (IPR) indicates which INRQ interrupt sources require interrupt service. The
interrupt mask register (IMR) allows the user to prevent any of the INRQ interrupt sources
from generating an interrupt request. The interrupt in-service register (ISR) provides a ca-
pability for nesting INRQ interrupt requests.
3.2.5.1 Global Interrupt Mode Register (GIMR)
The user normally writes the GIMR soon after a total system reset. The GIMR is initially
$0000 and is reset only upon a total system reset. If bits V7–V5 of the GIMR are not written
to specify an interrupt vector prior to the first interrupt condition, the interrupt controller will
pass the vector $0F (the uninitialized interrupt vector), regardless of the interrupt source.
MOD—Mode
IV7—Level 7 Interrupt Vector
IV6—Level 6 Interrupt Vector
IV1—Level 1 Interrupt Vector
3-24
MOD
15
This bit is valid in both normal and dedicated modes.
This bit is valid in both normal and dedicated modes.
This bit is valid in both normal and dedicated modes.
0 = Normal operational mode. Interrupt request lines are configured as IPL2–IPL0.
1 = Dedicated operational mode. Interrupt request lines are configured as IRQ7, IRQ6,
0 = Internal vector. The interrupt controller will provide the vector number for a level 7
1 = External vector. The interrupt controller will not provide the vector number for a lev-
0 = Internal vector. The interrupt controller will provide the vector number for a level 6
1 = External vector. The interrupt controller will not provide the vector number for a lev-
0 = Internal vector. The interrupt controller will provide the vector number for a level 1
1 = External vector. The interrupt controller will not provide the vector number for a lev-
IV7
14
and IRQ1.
interrupt during the interrupt acknowledge cycle.
el 7 interrupt.
interrupt during the interrupt acknowledge cycle.
el 6 interrupt.
interrupt acknowledge cycle.
el 1 interrupt.
IV6
13
IV1
12
11
—
ET7
10
MC68302 USER’S MANUAL
ET6
9
ET1
8
7
V7–V5
5
4
RESERVED
MOTOROLA
0
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