MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 113
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
The following list gives a step-by-step example of how to achieve the lowest possible power
using an external clock. For this example, an external wakeup signal is issued to the PB11
pin to exit the lowest power mode.
The low-power logic uses eight bits in the SCR.
LPCD4–LPCD0—Low-power Clock Divider Selects
LPEN—Low-power Enable
MOTOROLA
1. Set the lower byte of the SCR (location $F7) to $A0. This sets the LPREC bit and the
2. Disable all interrupts except PB11 in the IMR.
3. Turn off any unneeded peripherals, such as the SCCs, by clearing the ENR and ENT
4. Start off a timer now to toggle a TOUT pin in approximately 20 clocks. Do not wait for
5. Execute the STOP instruction. The IMP is now safely in the lowest power mode.
6. Use the toggled TOUT pin to switch the EXTAL clock rate to approximately 50 kHz.
7. Power consumption is now the lowest.
8. A wakeup signal comes from the system.
9. The wakeup signal switches the clock frequency back to the 8–16.67-MHz range and
10. The IMP generates the PB11 interrupt, and a M68000 core reset is generated.
11. After the IMP is reset, software processing continues from the exception vector table
The low-power clock divider select bits (LPCD4—LPCD0) specify the divide ratio of the
low-power clock divider equal to LPCD4—LPCD0 + 1. The system clock is divided by 2,
then divided by the clock divider value (1 to 32). Thus, a divide ratio of 2 to 64 (LPCD4—
LPCD0 0 to 31) can be selected. After a system reset, these bits default to zero.
After a system reset, this bit defaults to zero to disable the low-power modes.
0 = The low-power modes are disabled.
1 = The low-power modes are enabled.
LPEN bits only.
bits. Also, turn off any unneeded baud rate generators by setting the EXTC bits in the
SCON registers. This procedure can save as much as 4 mA per SCC at 16.67 MHz.
(EXTC is cleared by default on after reset.)
this to occur, but continue on to the next step.
Ensure no glitches occur on the EXTAL signal which exceed the maximum clock fre-
quency.
pulls the PB11 pin low. These two events can happen simultaneously.
reset vector address. The M68000 is reset, but the rest of the IMP retains its state.
pendix A SCC Performance). Also, the minimum 1:2.5 serial to
CLKO clock ratio must be maintained at all times.
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-63
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