MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 239
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
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OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET +6
The first word of the Rx BD contains control and status bits. Bits 15–13 are written by the
user before the buffer is linked to the Rx BD table, and bits 1 and 3 are set by the IMP fol-
lowing message reception. Bit 15 is set by the M68000 core when the buffer is available to
the V.110 controller and is cleared by the V.110 controller after filling the buffer.
E—Empty
X—External Buffer
W—Wrap (Final BD in Table)
Bits 12–4, 2, 0—Reserved for future use.
SE—Synchronization Error
OV—Overrun
MOTOROLA
A frame with a synchronization error was received. A synchronization error is detected by
the V.110 controller when the MSB of a byte (except the all-zeros byte) is not one.
A receiver overrun occurred during message reception.
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with this BD is empty. This bit signifies that the BD and
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the V.110
reception has been aborted due to an error condition. The M68000 core is free to
examine or write to any fields of the BD.
its associated buffer are available to the V.110 controller. The M68000 core should
not write to any fields of this BD after it sets this bit. The empty bit will remain set
while the V.110 controller is currently filling the buffer with received data.
controller receives incoming data by placing it in the first BD in the table.
15
E
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
14
X
Figure 4-40. V.110 Receive Buffer Descriptor
13
W
12
—
RX BUFFER POINTER (24-bits used, upper 8 bits must be 0)
11
—
MC68302 USER’S MANUAL
10
—
NOTE
—
9
DATA LENGTH
—
8
—
7
—
6
Communications Processor (CP)
—
5
—
4
SE
3
—
2
OV
1
4-119
—
0
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