MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 386

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
D.6.8 SCC Configuration
SCC1 will be set according the rate adaptation protocol implemented. If V.120 is used, the
protocol should be set to HDLC. If V.110 is used, program SCC1 to V.110 (configured under
the DDCMP mode). The following values are suitable:
ues are suitable:
plexing SCC3 into lDL leaves the SCP pins available for the SCP port.) The following values
are suitable:
D-36
SCC2 will be set to handle a 9600 baud UART from a non-lSDN terminal. The following val-
SCC3 will be set to handle the HDLC frames of LAPD protocol over the D-channel. (Multi-
Configuration Register (SCONE)
Mode Register (SCM1) for V.120
Mode Register (SCM1) for V. 110
Sync Register (DSR1)
Sync Register (DSR1)
Mask Register (SCCM1)
Configuration Register (SCON2)
Mode Register (SCM2)
Sync Register (DSR2)
Mask Register (SCCM2)
Configuration Register (SCON3)
Mode Register (SCM3)
Sync Register (DSR3)
Mask Register (SCCM3)
In addition to programming the SCCs registers, the protocol-
specific parameter RAM of each SCC should be initialized by the
control software according to the protocol selected.
Register
Register
Register
MC68302 USER’S MANUAL
NOTE
$30FF
$000C
$040E
$7E7E
$30FF
$010D
$7E7E
$010C
$7E7E
$0100
$3000
Value
Value
Value
$1B
External receive and transmit clocks will be provid-
ed from the IDL through the serial Interface.
HDLC mode.
V.110 mode.
HDLC flag.
The mask should be set according to the interrupt
events handled.
Set internal receive and transmit clocks, 9600 baud
if 16.6-MHz parallel clock used.
UART mode, 8 bits, no parity
Bits 14-12 control stop-bit shaving.
The mask should be set in accordance with the in-
terrupt events the software wants to handle.
External receive and transmit clocks (will be pro-
vided from the IDL through the serial interface)
HDLC mode with retransmit option.
HDLC flag.
The mask should be set in accordance with the in-
terrupt events the software wants to handle.
V.110 sync pattern
Comments
Comments
Comments
MOTOROLA