MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 60

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
3.1.4.3 Address Sequencing
The manner in which the DAPR and SAPR are incremented during a transfer depends on
the programming of the SAPI and DAPI bits, the source and destination sizes (DSIZE and
SSIZE), and the system data bus width.
The IDMA will run at least two, and up to four, bus cycles to transfer each operand. With an
8-bit bus width, SSIZE and DSIZE are ignored, and each operand transfer requires two cy-
cles. With a 16-bit bus width, the number of bus cycles required to transfer each operand is
determined by DSIZE and SSIZE, whether the source and destination addresses are odd or
even, and whether the BCR equals one. When SSIZE and DSIZE both select either a byte
or word, there will be no operand packing, and the operand transfer will take two bus cycles.
One exception occurs when DSIZE and SSIZE are words and the address is odd. In this
case, there will be two (one byte each) memory cycles for each read or write at an odd ad-
dress. When both the source and destination addresses are odd, four bus cycles are re-
quired to transfer each operand. When SSIZE and DSIZE are not equal, the IDMA will
perform operand packing. If SSIZE is one byte, two read cycles are required to fetch the op-
erand. If DSIZE is one byte, two write cycles are required to store the operand.
When SAPI and/or DAPI are programmed to increment either SAPR or DAPR, the amount
(one or two) by which the address pointer increments depends upon DSIZE, SSIZE, and the
bus width.
When operating in a 16-bit bus environment with an 8-bit peripheral, the peripheral may be
placed on one-half of the bus (consecutive even or odd addresses only). In this case, SSIZE
(or DSIZE) must be set to 16 bit, and the IDMA will perform data packing. As a result, the
peripheral's addresses must be incremented twice after each peripheral bus cycle, which re-
sults in adding four to the address for each data transfer (two cycles per transfer). This is
consistent with the M68000 MOVEP instruction. If the 8-bit peripheral is to be arranged with
consecutive addresses, both SSIZE and DSIZE must be 8 bit.
Refer to Table 3-1 to see how the SAPR and DAPR will be incremented in all combinations.
Refer toTable 3-2 for more details on the IDMA bus cycles.
3-10
Width
16 Bit
16 Bit
16 Bit
16 Bit
Bus
8 Bit
Source
Word
Word
Size
Byte
Byte
X
Table 3-1. SAPR and DAPR Incrementing Rules
Destination
Word
Word
Size
Byte
Byte
X
MC68302 USER’S MANUAL
Increment
SAPR
+1
+1
+4
+2
+2
Increment
DAPR
+1
+1
+2
+4
+2
Read Byte—Write Byte
Packing Is Not Possible
Read Byte—Write Byte
Packing Is Not Desired
Read Byte, Read Byte —Write Word
Operand Packing
Read Word—Write Byte, Write Byte
Operand Unpacking
Read Word—Write Word
Description
Transfer
MOTOROLA