MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 93

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.5
Three supervisor registers define the operation of the instruction cache and local bus controller: the Cache
Control Register (CACR) and two Access Control Registers (ACR0, ACR1).
5.5.1
Table 5-3
The following list describes several key issues regarding the memory map table:
The access column indicates if the corresponding register allows both read/write functionality (R/W),
read-only functionality (R), or write-only functionality (W). If a read access to a write-only register is
attempted, zeros will be returned. If a write access to a read-only register is attempted the access will be
ignored and no write will occur.
Freescale Semiconductor
CACR[31] CACR[10]
•
•
•
0
0
1
1
1
The Cache Control Register and Access Control Registers can only be accessed in supervisor mode
using the MOVEC instruction with an Rc value of $002, $004 and $005, respectively.
Addresses not assigned to the registers and undefined register bits are reserved for future
expansion. Write accesses to these reserved address spaces and reserved register bits have no
effect; read accesses will return zeros.
The reset value column indicates the initial value of the register at reset. Certain registers may
contain random values after reset.
Instruction Cache Memory Map and Register Definitions
shows the memory map of the Instruction cache and access control registers.
MOVEC with $002
MOVEC with $004
MOVEC with $005
Instruction Cache Registers Memory Map
X
0
1
0
1
Address
Table 5-2. Instruction Cache Operation as Defined by CACR [31,10]
Type of Instruction
Noncacheable
Noncacheable
Cacheable
Fetch
N/A
N/A
Table 5-3. Memory Map of I-Cache Registers
CACR
Name
ACR0
ACR1
MCF5253 Reference Manual, Rev. 1
Instruction cache is completely disabled; all fetches are word, longword in size
All fetches are word, longword in size
Fetch size is defined by
written into the memory array
All fetches are longword in size, and not loaded into the line-fill buffer
Fetch size is defined by
written into the memory array
Width
32
32
32
Cache Control Register
Access Control Register 0
Access Control Register 1
Description
Table 5-1
Table 5-1
and loaded into the line-fill buffer, but are never
Description
and contents of the line-fill buffer can be
$0000
$0000
$0000
Value
Reset
Access
W
W
W
Instruction Cache
5-5