MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 376

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Background Debug Mode (BDM) Interface
next instruction needs to display captured values on DDATA, the pipeline stalls (PST = $0) until space is
available in the FIFO.
20.2.1.6
The unique encoding is generated whenever the return-from-exception (RTE) instruction is executed.
20.2.1.7
These encodings serve as markers to indicate the number of bytes to be displayed on the DDATA port on
subsequent clock cycles. This encoding is driven onto the PST port one processor cycle before the actual
data is displayed on DDATA. When PST outputs a $8/$9/$A/$B marker value, the DDATA port outputs
1/2/3/4 bytes of captured data respectively on consecutive processor cycles.
20.2.1.8
This encoding is displayed during normal exception processing. Exceptions which enter emulation mode
(debug interrupt, or optionally trace) generate a different encoding. Because this encoding defines a
multicycle mode, the PST outputs are driven with this value until exception processing is completed.
20.2.1.9
This encoding is displayed during emulation mode (debug interrupt, or optionally trace). Because this
encoding defines a multicycle mode, the PST outputs are driven with this value until exception processing
is completed.
20.2.1.10 Processor Stopped (PST = $E)
This encoding is generated as a result of the STOP instruction. The ColdFire processor remains in the
stopped state until an interrupt occurs. Because this encoding defines a multicycle mode, the PST outputs
are driven with this value until the stopped mode is exited.
20.2.1.11 Processor Halted (PST = $F)
This encoding is generated when the ColdFire processor is halted (Refer to
Because this encoding defines a multicycle mode, the PST outputs are driven with this value until the
processor is restarted, or reset.
20.3
Background debug mode (BDM) implements a low-level system debugger in the microprocessor
hardware. Communication with the development system is handled through a dedicated, high-speed,
full-duplex serial command interface. The BDM features are as follows:
20-6
•
ColdFire implements the BDM controller in a dedicated hardware module. Although some BDM
operations do require the CPU to be halted (For example, CPU register accesses), other BDM
commands such as memory accesses can be executed while the processor is running.
Background-Debug Mode (BDM)
Begin Execution of RTE Instruction (PST = $7)
Begin Data Transfer (PST = $8–$B)
Exception Processing (PST = $C)
Emulator Mode Exception Processing (PST = $D)
MCF5253 Reference Manual, Rev. 1
Section 20.3.1, “CPU
Freescale Semiconductor
Halt.”)