MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 397

• Manufacturer Part Number: MCF5253VM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253VM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

the exact trigger response also programmable. The debug module programming model is accessible from
either the external development system using the serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction.
20.4.1
The breakpoint hardware can be configured to respond to triggers in several ways. The desired response
is programmed into the Trigger Definition Register (TDR). In all situations where a breakpoint triggers,
an indication is provided on the DDATA output port, when not displaying captured operands or branch
addresses, as shown in
The breakpoint status is also posted in the CSR.
The BDM instructions load and configure the desired breakpoints using the appropriate registers. As the
system operates, a breakpoint trigger generates a response as defined in the TDR. If the system can tolerate
the processor being halted, a BDM-entry can be used. With the TRC bits of the TDR equal to $1, the
breakpoint trigger causes the core to halt as reflected in the PST = $F status.
If the processor core cannot be halted, the special debug interrupt can be used. With this configuration,
TRC bits of the TDR equal to $2, the breakpoint trigger is converted into a debug interrupt to the processor.
This interrupt is treated higher than the nonmaskable level 7 interrupt request. As with all interrupts, it is
made pending until the processor reaches a sample point, which occurs once per instruction. Again, the
hardware forces the PC breakpoint to occur immediately (before the execution of the targeted instruction).
This is possible because the PC breakpoint comparison is enabled at the same time the interrupt sampling
occurs. For the address and data breakpoints, the reporting is considered imprecise because several
additional instructions may be executed after the triggering address or data is seen.
Once the debug interrupt is recognized, the processor aborts execution and initiates exception processing.
At the initiation of the exception processing, the core enters emulator mode. After the standard 8-byte
Freescale Semiconductor
Theory of Operation
For PC breakpoints, the halt occurs before the targeted instruction is
executed. For address and data breakpoints, the processor may have
executed several additional instructions. As a result, trigger reporting is
considered imprecise.
Table
Table 20-17. DDATA[3:0], CSR[31:28] Breakpoint Response
DDATA[3:0], CSR[31:28]
20-17.
$000x
$001x
$010x
$101x
$110x
All other encodings are reserved for future use.
MCF5253 Reference Manual, Rev. 1
NOTE
Waiting for Level 1 Breakpoint
Waiting for Level 2 Breakpoint
Level 1 Breakpoint Triggered
Level 2 Breakpoint Triggered
No Breakpoints Enabled
Breakpoint Status
Background Debug Mode (BDM) Interface
20-27