MCF5253VM140J Freescale Semiconductor, MCF5253VM140J Datasheet - Page 371
MCF5253VM140J
Manufacturer Part Number
MCF5253VM140J
Description
IC MCU 2.1MIPS 140MHZ 225MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr
Datasheets
1.MCF5253VM140J.pdf
(34 pages)
2.MCF5253VM140J.pdf
(8 pages)
3.MCF5253VM140J.pdf
(648 pages)
4.MCF5253VM140J.pdf
(2 pages)
Specifications of MCF5253VM140J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
225-MAPBGA
Processor Series
MCF525x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5253VM140J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 20
Background Debug Mode (BDM) Interface
This chapter details the MCF5253 hardware debug support. The topics discussed are real-time trace
support, background debug mode (BDM), and real-time debug support. The memory map, register
descriptions and debug support operation are provided.
The MCF5253 implements an enhanced debug architecture. The original design plus these enhancements
is known as Revision A (or Rev. A). The enhanced functionality is clearly identified in this chapter. The
Rev. A enhancements are backward compatible with the original ColdFire debug definition.
The general topic of debug support is divided into three separate areas:
The logic required to support these three areas is contained in a debug module as shown in
20.1
This section describes signals associated with the debug module. All ColdFire debug signals are
unidirectional and are related to the rising-edge of the processor core’s clock signal.
Freescale Semiconductor
1. Real-Time Trace Support
2. Background Debug Mode (BDM)
3. Real-Time Debug Support
Debug Support Signals
To enable Debug Mode, TEST[2:0] pins must be = 001.
CONTROL
BKPT
Figure 20-1. Processor/Debug Module Interface
COLDFIRE CPU
TRACE PORT
DDATA, PST, PSTCLK
MCF5253 Reference Manual, Rev. 1
MODULE
CORE
DEBUG
NOTE
COMMUNICATION PORT
DSCLK, DSI, DSO
HIGH SPEED
LOCAL BUS
Figure
20-1.
20-1
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